URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_uart.v] - Diff between revs 104 and 105

Rev 104	Rev 105
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 104 $`	`// $Rev: 105 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $`	`// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`ifdef OMSP_NO_INCLUDE	`ifdef OMSP_NO_INCLUDE
`else	`else
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"
`endif	`endif
Line 90...	Line 90...

`// Synchronize RXD input & buffer`	`// Synchronize RXD input & buffer`
`//--------------------------------`	`//--------------------------------`
`reg [3:0] rxd_sync;`	`reg [3:0] rxd_sync;`
`always @ (posedge mclk or posedge por)`	`always @ (posedge mclk or posedge por)`
`if (por) rxd_sync <= 4'h0;`	`if (por) rxd_sync <= 4'hf;`
`else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};`	`else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};`

`// Majority decision`	`// Majority decision`
`//------------------------`	`//------------------------`
`reg rxd_maj;`	`reg rxd_maj;`