URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_execution_unit.v] - Diff between revs 176 and 190

Rev 176	Rev 190
Line 34...	Line 34...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 176 $`	`// $Rev: 190 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2013-01-30 22:22:50 +0100 (Wed, 30 Jan 2013) $`	`// $LastChangedDate: 2013-07-30 22:19:34 +0200 (Tue, 30 Jul 2013) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`ifdef OMSP_NO_INCLUDE	`ifdef OMSP_NO_INCLUDE
`else	`else
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"
`endif	`endif
Line 336...	Line 336...

wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :	wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :
`~inst_bw ? 2'b11 :`	`~inst_bw ? 2'b11 :`
`alu_out_add[0] ? 2'b10 : 2'b01;`	`alu_out_add[0] ? 2'b10 : 2'b01;`

`assign mb_en = mb_rd_det \| mb_wr_det;`	assign mb_en = mb_rd_det \| (mb_wr_det & ~inst_alu[`EXEC_NO_WR]);

`assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk;`	`assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk;`