| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 193 $
|
// $Rev: 202 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2013-12-17 21:16:33 +0100 (Tue, 17 Dec 2013) $
|
// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
//`define OMSP_NO_INCLUDE
|
//`define OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_undefines.v"
|
`include "openMSP430_undefines.v"
|
| Line 131... |
Line 131... |
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define WATCHDOG
|
`define WATCHDOG
|
|
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
|
// Include/Exclude DMA interface support
|
|
//-------------------------------------------------------
|
|
//`define DMA_IF_EN
|
|
|
|
|
|
//-------------------------------------------------------
|
// Include/Exclude Non-Maskable-Interrupt support
|
// Include/Exclude Non-Maskable-Interrupt support
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define NMI
|
`define NMI
|
|
|
|
|
| Line 775... |
Line 781... |
`define BRK_I_EN 3
|
`define BRK_I_EN 3
|
`define BRK_RANGE 4
|
`define BRK_RANGE 4
|
|
|
// Basic clock module: BCSCTL1 Control Register
|
// Basic clock module: BCSCTL1 Control Register
|
`define DIVAx 5:4
|
`define DIVAx 5:4
|
|
`define DMA_CPUOFF 0
|
|
`define DMA_SCG0 1
|
|
`define DMA_SCG1 2
|
|
`define DMA_OSCOFF 3
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
// Basic clock module: BCSCTL2 Control Register
|
`define SELMx 7
|
`define SELMx 7
|
`define DIVMx 5:4
|
`define DIVMx 5:4
|
`define SELS 3
|
`define SELS 3
|
| Line 805... |
Line 815... |
//
|
//
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
//======================================
|
//======================================
|
|
|
// Debug interface: CPU version
|
// Debug interface: CPU version
|
`define CPU_VERSION 3'h2
|
// 1 - FPGA support only (Pre-BSD licence era)
|
|
// 2 - Add ASIC support
|
|
// 3 - Add DMA interface support
|
|
`define CPU_VERSION 3'h3
|
|
|
// Debug interface: Software breakpoint opcode
|
// Debug interface: Software breakpoint opcode
|
`define DBG_SWBRK_OP 16'h4343
|
`define DBG_SWBRK_OP 16'h4343
|
|
|
// Debug UART interface auto data synchronization
|
// Debug UART interface auto data synchronization
|
