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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [include/] [board.h] - Diff between revs 389 and 405

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Rev 389 Rev 405
Line 23... Line 23... 
 * 3 - JB ORSoC board 2
 
 * 3 - JB ORSoC board 2
 
 * 4 - Unassigned
 
 * 4 - Unassigned
 
 */
 
 */
 
#define IPCONFIG                 3
 
#define IPCONFIG                 3
 
 
 
 
 
#define SDC_CONTROLLER_BASE 0x9e000000
 
 
 
 
 
 
 
#if BOARD==0
 
#if BOARD==0
 
// Nibbler on bender1
 
// Nibbler on bender1
 
 
 
 
 
#  define FLASH_BASE_ADDR         0xf0000000
 
#  define FLASH_BASE_ADDR         0xf0000000
 
#  define FLASH_SIZE              0x02000000
 
#  define FLASH_SIZE              0x02000000
Line 52... Line 50... 
#  define IN_CLK                  50000000
 
#  define IN_CLK                  50000000
 
#  define FLASH_ORG_16_2          1
 
#  define FLASH_ORG_16_2          1
 
#  define BOARD_DEF_NAME          "marvin"
 
#  define BOARD_DEF_NAME          "marvin"
 
 
 
 
 
#elif BOARD==2
 
#elif BOARD==2
 
//ORSoC usbethdev board
 
//ORSoC ordb1a3pe1500
 
 
 
 
 
#  define FLASH_BASE_ADDR         0xf0000000
 
#  define FLASH_BASE_ADDR         0xf0000000
 
#  define FLASH_SIZE              0x04000000
 
#  define FLASH_SIZE              0x04000000
 
#  define FLASH_BLOCK_SIZE        0x00040000
 
#  define FLASH_BLOCK_SIZE        0x00040000
 
#  define START_ADD               0x0
 
#  define START_ADD               0x0
 
#  define SDRAM_SIZE              0x02000000
 
#  define SDRAM_SIZE              0x02000000
Line 119... Line 116... 
#define BOARD_DEF_GW            0xc0a86401 // 192.168.100.1
 
#define BOARD_DEF_GW            0xc0a86401 // 192.168.100.1
 
#define BOARD_DEF_TBOOT_SRVR    0xc0a864e3 //"192.168.100.227"
 
#define BOARD_DEF_TBOOT_SRVR    0xc0a864e3 //"192.168.100.227"
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MACADDR0            0xad
 
#define ETH_MACADDR0            0x00
 
#define ETH_MACADDR1            0xda
 
#define ETH_MACADDR1            0x12
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR5            0x9b
 
#define ETH_MACADDR5            0x9b
 
 
 
 
Line 142... Line 139... 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR5            0x9c
 
#define ETH_MACADDR5            0x9c
 
 
 
 
 
#elif IPCONFIG==3 // ORSoC LAN
 
#elif IPCONFIG==3 // JB ORSoC board 2
 
 
 
 
 
#define BOARD_DEF_IP            0xc0a80103 // 192.168.1.3
 
#define BOARD_DEF_IP            0xc0a8015a // 192.168.1.90
 
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
 
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
 
#define BOARD_DEF_GW            0xc0a80101 // 192.168.1.1
 
#define BOARD_DEF_GW            0xc0a80101 // 192.168.1.1
 
#define BOARD_DEF_TBOOT_SRVR    0xc0a80101 // 192.168.1.1
 
#define BOARD_DEF_TBOOT_SRVR    0xc0a80108 // 192.168.1.8
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MACADDR0            0xad
 
#define ETH_MACADDR0            0x00
 
#define ETH_MACADDR1            0xaa
 
#define ETH_MACADDR1            0x12
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR5            0x9d
 
#define ETH_MACADDR5            0x9d
 
 
 
 
Line 167... Line 164... 
#define BOARD_DEF_GW            0x0a010101 // 10.1.1.1
 
#define BOARD_DEF_GW            0x0a010101 // 10.1.1.1
 
#define BOARD_DEF_TBOOT_SRVR    0x0a010101 // 10.1.1.1
 
#define BOARD_DEF_TBOOT_SRVR    0x0a010101 // 10.1.1.1
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_IMAGE_NAME    "boot.img"
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define BOARD_DEF_LOAD_SPACE    0xa00000
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MDIOPHYADDR         0x00
 
#define ETH_MACADDR0            0xad
 
#define ETH_MACADDR0            0x00
 
#define ETH_MACADDR1            0xaa
 
#define ETH_MACADDR1            0x01
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR2            0x34
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR3            0x56
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR4            0x78
 
#define ETH_MACADDR5            0x9d
 
#define ETH_MACADDR5            0x9e
 
 
 
 
 
#endif
 
#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
#define UART_BAUD_RATE          115200
 
#define UART_BAUD_RATE          115200
 
 
 
 
 
#define TICKS_PER_SEC           100
 
#define TICKS_PER_SEC           100
 
 
 
 
 
 
 
 
Line 211... Line 206... 
#define CRT_BASE_ADDR           0x97000000
 
#define CRT_BASE_ADDR           0x97000000
 
#define ATA_BASE_ADDR           0x9e000000
 
#define ATA_BASE_ADDR           0x9e000000
 
#define KBD_BASE_ADD            0x94000000
 
#define KBD_BASE_ADD            0x94000000
 
#define KBD_IRQ                 5
 
#define KBD_IRQ                 5
 
 
 
 
 
 
 
#define SDC_CONTROLLER_BASE     0x9e000000
 
 
 
 
 
#define SANCHO_BASE_ADD         0x98000000
 
#define SANCHO_BASE_ADD         0x98000000
 
/*  Address for ETH_DATA */
 
/*  Address for ETH_DATA */
 
#define ETH_DATA_BASE           (SDRAM_SIZE - (0x600 * 128)) 
#define ETH_DATA_BASE           (SDRAM_SIZE - (0x600 * 128)) 
 
 
 
 
#define CRT_ENABLED             0
 
#define CRT_ENABLED             0

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