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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 419 and 463

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Rev 419	Rev 463
Line 11...	Line 11...
`.extern _dst_end`	`.extern _dst_end`
`.extern int_main`	`.extern int_main`
`.extern int_error`	`.extern int_error`
`.extern tick_interrupt`	`.extern tick_interrupt`
`.extern _crc32`	`.extern _crc32`
	`.extern _bstart`
	`.extern _bend`
`.global _calc_mycrc32`	`.global _calc_mycrc32`
`.global _mycrc32`	`.global _mycrc32`
`.global _mysize`	`.global _mysize`

`.section .stack, "aw", @nobits`	`.section .stack, "aw", @nobits`
Line 52...	Line 53...
`l.addi r1,r1,4`	`l.addi r1,r1,4`
`.endif`	`.endif`

`.org 0x100`	`.org 0x100`

`.if IN_FLASH`
`.section .reset, "ax"`
`.else`
`.section .vectors, "ax"`	`.section .vectors, "ax"`
`.endif`

`_reset:`	`_reset:`
`l.movhi r0, 0`	`l.movhi r0, 0`
`/* Clear status register, set supervisor mode */`	`/* Clear status register, set supervisor mode */`
`l.ori r1, r0, SPR_SR_SM`	`l.ori r1, r0, SPR_SR_SM`
Line 71...	Line 68...
`l.movhi r3,hi(_start)`	`l.movhi r3,hi(_start)`
`l.ori r3,r3,lo(_start)`	`l.ori r3,r3,lo(_start)`
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`

`.if IN_FLASH`
`.section .vectors, "ax"`
`.org 0x200`
`.else`
`.org (0x200 - 0x100 + _reset)`	`.org (0x200 - 0x100 + _reset)`
`.endif`
`_buserr:`	`_buserr:`
`.if TRAP_ON_ERROR`	`.if TRAP_ON_ERROR`
`/* Just trap */`	`/* Just trap */`
`l.trap 0`	`l.trap 0`
`.endif`	`.endif`
Line 94...	Line 87...
`.if PRINT_AND_RESET_ON_ERROR`	`.if PRINT_AND_RESET_ON_ERROR`
`l.mfspr r4, r0, SPR_EPCR_BASE`	`l.mfspr r4, r0, SPR_EPCR_BASE`
`l.j _int_error /* This will reset */`	`l.j _int_error /* This will reset */`
`l.ori r3, r0, 0x2`	`l.ori r3, r0, 0x2`
`.endif`	`.endif`
`.if IN_FLASH`
`.section .vectors, "ax"`
`.org 0x500`
`.else`
`.org (0x500 - 0x100 + _reset)`	`.org (0x500 - 0x100 + _reset)`
`.endif`
`_tickint:`	`_tickint:`
`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`	`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
`/* Simply load timer_ticks variable and increment */`	`/* Simply load timer_ticks variable and increment */`
`.extern _timer_ticks`	`.extern _timer_ticks`
`l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/`	`l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/`
Line 120...	Line 109...
`l.lwz r25, 0(r1)`	`l.lwz r25, 0(r1)`
`l.lwz r26, 4(r1)`	`l.lwz r26, 4(r1)`
`l.addi r1, r1, 136`	`l.addi r1, r1, 136`
`l.rfe`	`l.rfe`

`.if IN_FLASH`
`.section .vectors, "ax"`
`.org 0x600`
`.else`
`.org (0x600 - 0x100 + _reset)`	`.org (0x600 - 0x100 + _reset)`
`.endif`
`_alignerr:`	`_alignerr:`
`.if TRAP_ON_ERROR`	`.if TRAP_ON_ERROR`
`/* Just trap */`	`/* Just trap */`
`l.trap 0`	`l.trap 0`
`.endif`	`.endif`
Line 144...	Line 129...
`l.mfspr r4, r0, SPR_EPCR_BASE`	`l.mfspr r4, r0, SPR_EPCR_BASE`
`l.j _int_error /* This will reset */`	`l.j _int_error /* This will reset */`
`l.ori r3, r0, 0x6`	`l.ori r3, r0, 0x6`
`.endif`	`.endif`

`.if IN_FLASH`
`.org 0x700`
`.else`
`.org (0x700 - 0x100 + _reset)`	`.org (0x700 - 0x100 + _reset)`
`.endif`
`_illinsn:`	`_illinsn:`
`.if TRAP_ON_ERROR`	`.if TRAP_ON_ERROR`
`/* Just trap */`	`/* Just trap */`
`l.trap 0`	`l.trap 0`
`.endif`	`.endif`
Line 166...	Line 148...
`.if PRINT_AND_RESET_ON_ERROR`	`.if PRINT_AND_RESET_ON_ERROR`
`l.mfspr r4, r0, SPR_EPCR_BASE`	`l.mfspr r4, r0, SPR_EPCR_BASE`
`l.j _int_error /* This will reset */`	`l.j _int_error /* This will reset */`
`l.ori r3, r0, 0x7`	`l.ori r3, r0, 0x7`
`.endif`	`.endif`
`.if IN_FLASH`
`.org 0x800`
`.else`
`.org (0x800 - 0x100 + _reset)`	`.org (0x800 - 0x100 + _reset)`
`.endif`
`_userint:`	`_userint:`
`l.addi r1,r1,-256 /(128 + 128) /`	`l.addi r1,r1,-256 /(128 + 128) /`
`l.sw 0x0(r1),r2`	`l.sw 0x0(r1),r2`
`l.addi r2, r1, 256`	`l.addi r2, r1, 256`
`l.sw 0x4(r1), r3`	`l.sw 0x4(r1), r3`
Line 183...	Line 162...
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`

`.section .text`	`.section .text`
`_start:`	`_start:`
`/* Copy form flash to sram */`
`.if IN_FLASH`
`l.movhi r3,hi(_src_beg)`
`l.ori r3,r3,lo(_src_beg)`
`l.movhi r4,hi(_vec_start)`
`l.ori r4,r4,lo(_vec_start)`
`l.movhi r5,hi(_vec_end)`
`l.ori r5,r5,lo(_vec_end)`
`l.sub r5,r5,r4`
`l.sfeqi r5,0`
`l.bf 2f`
`l.nop`
`1: l.lwz r6,0(r3)`
`l.sw 0(r4),r6`
`l.addi r3,r3,4`
`l.addi r4,r4,4`
`l.addi r5,r5,-4`
`l.sfgtsi r5,0`
`l.bf 1b`
`l.nop`
`2:`
`l.movhi r4,hi(_dst_beg)`
`l.ori r4,r4,lo(_dst_beg)`
`l.movhi r5,hi(_dst_end)`
`l.ori r5,r5,lo(_dst_end)`
`1: l.sfgeu r4,r5`
`l.bf 1f`
`l.nop`
`l.lwz r8,0(r3)`
`l.sw 0(r4),r8`
`l.addi r3,r3,4`
`l.bnf 1b`
`l.addi r4,r4,4`
`1:`
`l.addi r3,r0,0`
`l.addi r4,r0,0`
`3:`
`.endif`


`/* Instruction cache enable */`	`/* Instruction cache enable */`
`/* Check if IC present and skip enabling otherwise */`	`/* Check if IC present and skip enabling otherwise */`
`l.mfspr r24,r0,SPR_UPR`	`l.mfspr r24,r0,SPR_UPR`
`l.andi r26,r24,SPR_UPR_ICP`	`l.andi r26,r24,SPR_UPR_ICP`
Line 333...	Line 273...
`l.movhi r1,hi(_stack-4)`	`l.movhi r1,hi(_stack-4)`
`l.ori r1,r1,lo(_stack-4)`	`l.ori r1,r1,lo(_stack-4)`
`l.addi r2,r0,-3`	`l.addi r2,r0,-3`
`l.and r1,r1,r2`	`l.and r1,r1,r2`

	`/* Clear BSS */`
	`l.movhi r3, hi(_bstart)`
	`l.ori r3, r3, lo(_bstart)`
	`l.movhi r4, hi(_bend)`
	`l.ori r4, r4, lo(_bend)`
	`.L11:`
	`l.sw 0(r3),r0`
	`l.sfgtu r3, r4`
	`l.bnf .L11`
	`l.addi r3, r3, 4`


`l.movhi r3,hi(main)`	`l.movhi r3,hi(main)`
`l.ori r3,r3,lo(main)`	`l.ori r3,r3,lo(main)`
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 419 and 463