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OpenRISC 1200 IP Core%OpenRISC 1200 IP Core SpecificationsDamjan Lampret39@1b@<]@*pj@H

OpenRISC 1200 IP Core%OpenRISC 1200 IP Core SpecificationsDamjan LampretJulius Baxter42@rDg@<]@*pj
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OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.8
Aug, 2010




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.Table Of Contents

 TOC \o "1-2" \t "Headeing 1 Name;1" \h HYPERLINK  \l "_toc229"Table Of Contents        3
 HYPERLINK  \l "_toc289"Table Of Figures   5
 HYPERLINK  \l "_toc308"Table Of Tables     6
 HYPERLINK  \l "_toc345"1 7
Introduction 7
 HYPERLINK  \l "_toc351"OpenRISC Family       7
 HYPERLINK  \l "_toc357"OpenRISC 1200 8
 HYPERLINK  \l "_toc368"Features   8
 HYPERLINK  \l "_toc376"2 9
Architecture 9
 HYPERLINK  \l "_toc395"CPU/DSP       10
 HYPERLINK  \l "_toc464"Data Cache     13
 HYPERLINK  \l "_toc520"Instruction Cache       16
 HYPERLINK  \l "_toc573"Data MMU 18
 HYPERLINK  \l "_toc625"Instruction MMU   20
 HYPERLINK  \l "_toc677"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc688"Tick Timer     22
 HYPERLINK  \l "_toc700"Power Management Support 23
 HYPERLINK  \l "_toc753"Debug unit     23
 HYPERLINK  \l "_toc762"Clocks & Reset	24
 HYPERLINK  \l "_toc768"WISHBONE Interfaces	24
 HYPERLINK  \l "_toc773"3	26
Operation	26
 HYPERLINK  \l "_toc778"Reset	26
 HYPERLINK  \l "_toc794"CPU/DSP	26
 HYPERLINK  \l "_toc1635"Data Cache Operation	31
 HYPERLINK  \l "_toc1718"Instruction Cache Operation	34
 HYPERLINK  \l "_toc1766"Data MMU	36
 HYPERLINK  \l "_toc1903"Instruction MMU	40
 HYPERLINK  \l "_toc2027"Programmable Interrupt Controller	43
 HYPERLINK  \l "_toc2045"Tick Timer	43
 HYPERLINK  \l "_toc2051"Power Management	43
 HYPERLINK  \l "_toc2087"Debug Unit	45
 HYPERLINK  \l "_toc2101"Development Interface	45
 HYPERLINK  \l "_toc2348"4	49
Registers	49
 HYPERLINK  \l "_toc2353"Registers list	49
 HYPERLINK  \l "_toc3065"Register VR description	50
 HYPERLINK  \l "_toc3136"Register UPR description	51
 HYPERLINK  \l "_toc3338"Register CPUCFGR description	51
 HYPERLINK  \l "_toc3451"Register DMMUCFGR description	52
 HYPERLINK  \l "_toc3562"Register IMMUCFGR description	52
 HYPERLINK  \l "_toc3673"Register DCCFGR description	53
 HYPERLINK  \l "_toc3826"Register ICCFGR description	54
 HYPERLINK  \l "_toc3976"Register DCFGR description	54
 HYPERLINK  \l "_toc4025"5	56
IO ports	56
 HYPERLINK  \l "_toc4038"Instruction WISHBONE Master Interface	56
 HYPERLINK  \l "_toc4202"Data WISHBONE Master Interface	57
 HYPERLINK  \l "_toc4366"System Interface	57
 HYPERLINK  \l "_toc2101"Development Interface	58
 HYPERLINK  \l "_toc4610"Power Management Interface	58
 HYPERLINK  \l "_toc4783"Interrupt Interface	59
 HYPERLINK  \l "_toc4814"A	60
Core HW Configuration	60
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture	9
Figure 2. CPU/DSP Block Diagram	10
Figure 3. Block Diagram of Debug Unit	24
Figure 4. Power-Up and Reset Sequence	26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock	26
Figure 6. WISHBONE Write Cycle	31
Figure 7. WISHBONE Block Read Cycle	32
Figure 8. WISHBONE Block Read/Write Cycle	32
Figure 9. WISHBONE Block Read Cycle	35
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table	37
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table	40
Figure 12. Development Interface Cycles	46
Figure 13. Assertion of External Watchpoint Trigger	48
Figure 14. Core s Interfaces	56 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200	13
Table 2. Possible Instruction Cache Configurations of OR1200	16
Table 3. Possible Data TLB Configurations of OR1200	18
Table 4. Possible Instruction TLB Configurations of OR1200	20
Table 5. Block Diagram of the Interrupt Controller	22
Table 6. Power Consumption	23
Table 7: Instructions implemented in OR1200	27
Table 8. Execution Time of Integer Instructions	29
Table 9: Execution time of floating point instructions	29
Table 10. List of Implemented Exceptions	30
Table 11. Protection Attributes for Load/Store Accesses	38
Table 12.  Cached and uncached regions	39
Table 13. Protection Attributes for Instruction Fetch Accesses	41
Table 14.  Cached and uncached regions	42
Table 15. Development Interface Operation Commands	46
Table 16. Status of the Load/Store Unit	47
Table 17. Status of the Instruction Unit	47
Table 18. List of All Registers	50
Table 19. VR Register	51
Table 20. UPR Register	51
Table 21. CPUCFGR Register	52
Table 22. DMMUCFGR Register	52
Table 23. IMMUCFGR Register	53
Table 24. DCCFGR Register	54
Table 25. ICCFGR Register	54
Table 26. DCFGR Register	55
Table 27. Instruction WISHBONE Master Interface  Signals	57
Table 28. Data WISHBONE Master Interface  Signals	57
Table 29. System Interface Signals	58
Table 30. Development Interface	58
Table 31. Power Management Interface	59
Table 32. Interrupt Interface	59
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
 EMBED Microsoft Visio Drawing 
All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

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Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/DSP

CPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP.
OR1200 CPU/DSP implements only 32-bit part of the OpenRISC 1000 architecture. 64-bit part of the architecture as well as floating-point and vector operations are not implemented in OR1200.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 2. CPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see table TBD.

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.
Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back stratergies.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag. It can also be configured with 256 or 32 lines.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

 EMBED Microsoft Visio Drawing 

The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and   
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 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz}~ effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

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The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


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Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

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Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has several clock inputs. Clock input clk_cpu clocks CPU/DSP block and all other parts of the RISC that do not have separate clocks. Data cache is clocked by clk_dc, instruction cache is clocked by clk_ic, data MMU is clocked by clk_dmmu, instruction MMU is clocked by clk_immu and tick timer is clocked by clk_tt. All clocks must have the same phase and as low clock skew as possible.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

 EMBED  
Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

 EMBED  
Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at reset is definable at synthesis time. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/DSP

CPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.mfsprl.sllilf.sub.sYl.addcYl.movhil.sral.addil.mtsprl.srail.andl.mulYl.srll.andil.muliYl.srlil.bfl.nopl.subYl.bnfl.orl.swl.divYl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYl.macrcYl.shlf.sflt.sYl.msbYl.slllf.sfne.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3DivideNot implementedCompare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.


MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.

Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions

The OR1200 exception support does not include support for fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

 EMBED  
Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


 EMBED  
Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

In the OpenRISC 1200, the differs from the architecture specification. The PIC offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
        


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS512512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE1616Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS512512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE1616Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3230Number of interrupt inputs


OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 8/31/10

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OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.9
September, 2010




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.0.912/9/10Julius BaxterClarified supported parts of OR1K instruction set
Updated core clock input information
Fixed up reference to instruction execute stage cycle table
Added divide cycles to execute stage cycle table
Table Of Contents

 TOC \o "1-2" \t "Headeing 1 Name;1" \h HYPERLINK  \l "_toc245"Table Of Contents    3
 HYPERLINK  \l "_toc305"Table Of Figures   5
 HYPERLINK  \l "_toc324"Table Of Tables     6
 HYPERLINK  \l "_toc361"1 7
Introduction 7
 HYPERLINK  \l "_toc367"OpenRISC Family       7
 HYPERLINK  \l "_toc375"OpenRISC 1200 8
 HYPERLINK  \l "_toc386"Features   8
 HYPERLINK  \l "_toc394"2 9
Architecture 9
 HYPERLINK  \l "_toc413"CPU/DSP       10
 HYPERLINK  \l "_toc483"Data Cache     13
 HYPERLINK  \l "_toc539"Instruction Cache       16
 HYPERLINK  \l "_toc592"Data MMU 18
 HYPERLINK  \l "_toc644"Instruction MMU   20
 HYPERLINK  \l "_toc696"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc707"Tick Timer     22
 HYPERLINK  \l "_toc719"Power Management Support 23
 HYPERLINK  \l "_toc772"Debug unit     23
 HYPERLINK  \l "_toc781"Clocks & Reset	24
 HYPERLINK  \l "_toc787"WISHBONE Interfaces	24
 HYPERLINK  \l "_toc792"3	26
Operation	26
 HYPERLINK  \l "_toc797"Reset	26
 HYPERLINK  \l "_toc813"CPU/DSP	26
 HYPERLINK  \l "_toc1655"Data Cache Operation	31
 HYPERLINK  \l "_toc1738"Instruction Cache Operation	34
 HYPERLINK  \l "_toc1786"Data MMU	36
 HYPERLINK  \l "_toc1923"Instruction MMU	40
 HYPERLINK  \l "_toc2047"Programmable Interrupt Controller	43
 HYPERLINK  \l "_toc2065"Tick Timer	43
 HYPERLINK  \l "_toc2071"Power Management	43
 HYPERLINK  \l "_toc2107"Debug Unit	45
 HYPERLINK  \l "_toc2121"Development Interface	45
 HYPERLINK  \l "_toc2368"4	49
Registers	49
 HYPERLINK  \l "_toc2373"Registers list	49
 HYPERLINK  \l "_toc3085"Register VR description	50
 HYPERLINK  \l "_toc3156"Register UPR description	51
 HYPERLINK  \l "_toc3358"Register CPUCFGR description	51
 HYPERLINK  \l "_toc3471"Register DMMUCFGR description	52
 HYPERLINK  \l "_toc3582"Register IMMUCFGR description	52
 HYPERLINK  \l "_toc3693"Register DCCFGR description	53
 HYPERLINK  \l "_toc3846"Register ICCFGR description	54
 HYPERLINK  \l "_toc3996"Register DCFGR description	54
 HYPERLINK  \l "_toc4045"5	56
IO ports	56
 HYPERLINK  \l "_toc4058"Instruction WISHBONE Master Interface	56
 HYPERLINK  \l "_toc4222"Data WISHBONE Master Interface	57
 HYPERLINK  \l "_toc4386"System Interface	57
 HYPERLINK  \l "_toc2121"Development Interface	58
 HYPERLINK  \l "_toc4630"Power Management Interface	58
 HYPERLINK  \l "_toc4803"Interrupt Interface	59
 HYPERLINK  \l "_toc4834"A	60
Core HW Configuration	60
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture	9
Figure 2. CPU/DSP Block Diagram	10
Figure 3. Block Diagram of Debug Unit	24
Figure 4. Power-Up and Reset Sequence	26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock	26
Figure 6. WISHBONE Write Cycle	31
Figure 7. WISHBONE Block Read Cycle	32
Figure 8. WISHBONE Block Read/Write Cycle	32
Figure 9. WISHBONE Block Read Cycle	35
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table	37
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table	40
Figure 12. Development Interface Cycles	46
Figure 13. Assertion of External Watchpoint Trigger	48
Figure 14. Core s Interfaces	56 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200	13
Table 2. Possible Instruction Cache Configurations of OR1200	16
Table 3. Possible Data TLB Configurations of OR1200	18
Table 4. Possible Instruction TLB Configurations of OR1200	20
Table 5. Block Diagram of the Interrupt Controller	22
Table 6. Power Consumption	23
Table 7: Instructions implemented in OR1200	27
Table 8. Execution Time of Integer Instructions	29
Table 9: Execution time of floating point instructions	29
Table 10. List of Implemented Exceptions	30
Table 11. Protection Attributes for Load/Store Accesses	38
Table 12.  Cached and uncached regions	39
Table 13. Protection Attributes for Instruction Fetch Accesses	41
Table 14.  Cached and uncached regions	42
Table 15. Development Interface Operation Commands	46
Table 16. Status of the Load/Store Unit	47
Table 17. Status of the Instruction Unit	47
Table 18. List of All Registers	50
Table 19. VR Register	51
Table 20. UPR Register	51
Table 21. CPUCFGR Register	52
Table 22. DMMUCFGR Register	52
Table 23. IMMUCFGR Register	53
Table 24. DCCFGR Register	54
Table 25. ICCFGR Register	54
Table 26. DCFGR Register	55
Table 27. Instruction WISHBONE Master Interface  Signals	57
Table 28. Data WISHBONE Master Interface  Signals	57
Table 29. System Interface Signals	58
Table 30. Development Interface	58
Table 31. Power Management Interface	59
Table 32. Interrupt Interface	59
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
 EMBED Microsoft Visio Drawing 
All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

However, at present the OR1200 is the only major RTL implementation of the OR1K architecture spec, and the OR1200 name has stuck, despite the high level of reconfigurability possible that would, strictly speaking, mean the core is either a OR1000, OR1300, etc. So, despite the various features that may or may not be implemented, the core is still only referred to as the OR1200.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B3 compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/FPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP. Not pictured are the FPU components.
OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction set. No ORBIS64, ORFBX64 or ORVDX64 instructions are  implemented in OR1200.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 2. CPU/FPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see Table 8. Execution Time of Integer Instructions .

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.

Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/FPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back stratergies.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied (written back) with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag. It can also be configured with 256 or 32 lines.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical addres       
Uj UjE UjUjcUjUjU0JjUUClnNPRlnpr

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
$&(*\^`&(*LNPR.024fjUjUj4Uj
UjN
UjUjhUjUjU0JUEfhj$&(*\^`PRT

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~8s translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

 EMBED Microsoft Visio Drawing 

The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

 EMBED Microsoft Visio Drawing 

The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


 EMBED Microsoft Visio Drawing 
Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has a clock input each for the instruction and data Wishbone interface logic, and for the CPU core. Clock input clk_cpu clocks everything inside the Wishbone interfaces. Data Wishbone interface is clocked by dwb_clk_i, instruction Wishbone interface is clocked by iwb_clk_i.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

 EMBED  
Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

 EMBED  
Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at reset is definable at synthesis time. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/FPU/DSP

CPU/FPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.mfsprl.sllilf.sub.sYl.addcYl.movhil.sral.addil.mtsprl.srail.andl.mulYl.srll.andil.muliYl.srlil.bfl.nopl.subYl.bnfl.orl.swl.divYl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYl.macrcYl.shlf.sflt.sYl.msbYl.slllf.sfne.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3Divide2Compare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.


MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
Care should be taken when executing l.macrc (MAC read and clear) too soon after the final l.mac instruction as the operation may still be underway and the result will not be valid in time. It is recommended at least 3 other instructions (or just l.nops) are inserted between the final l.mac and l.macrc.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.

Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions

The OR1200 exception support does not include support for fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

 EMBED  
Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

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Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


 EMBED  
Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

The PIC implementation in the OR1200  differs from the architecture specification. The PIC instead offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
      


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS512512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE1616Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS512512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE1616Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3230Number of interrupt inputs


OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 9/12/10

 HYPERLINK "http://www.opencores.org/"www.opencores.org       Rev 0.9 Preliminary  PAGE 61 of  NUMPAGES \*Arabic 61







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Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CLOCK   clk_risc
!
PERIODE 1
DUTY    50
CORGROUP        $$CLK_RISC_BufferRising
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_RISC_BufferRisingFalling
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_I_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_RISC_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
SIGNAL  dbg_wp_o[11]
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRising
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      0        1750    1750            1       0        DR      0
E1      1       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E2      0        4750    4750            1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_bp_o
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      0        2750    2750            1       0        DR      0
Percent 100
E1      1       4750    4750    If Enabled      1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
SIGNAL  dbg_ewt_i
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_RISC_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      0        1250    1250            1       0        DR      0
!
E1      1       3750    3750            1       0        DR      0
E2      0        4750    4750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
MARKER  MARK10
ATTACH  dbg_wp_o[11]    NULL    S1
CORGROUP        $$CLK_RISC_BufferRising
TIME    1610.903040
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_RISC_BufferFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_RISC_BufferRisingFalling
COMMENT aaa
Percent 100
!
!
MARKER  MARK20
CORGROUP        $$CLK_RISC_BufferRising
ATTACH  dbg_bp_o        NULL    S2
Percent 100
TIME    2644.928640
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_RISC_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_RISC_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$clk_risc_BufferRising
FQ/   %8&" WMFCcR P3PSxU>FQ/ EMFPSXVISIODrawing
Percent 100
 Y=&%%V0JJJJ%(%RL Arialdx		_VarMemberFlagsVB_Var@?>=<;:98%T+.g=*A*A+.
!
L`Context ID          T|5>\M*A*A5>L\(4 bits)&%%V0}JJ}J}J%(%RL Arial%T.<=*A*A.LpPage Index Level 1	T|>M*A*A>L\(8 bits)&%%V0}iJ}JiJi}}J%(%RL Arial%T.(=*A*A.LpPage Index Level 2  T> M*A*A>     L`(11 bits)&%%V0iUJiJUJUiiJ%(%RL Arial%T.=*A*A.LdPage Offset     
T>M*A*A>     L`(13 bits)RL Arial%TX"*A*ALP35RL Arial%(%TX"*A*ALP31%
(RL Arial%TXbo"*A*AbLP24%
(RL Arial'xx
'#
CORGROUP        $$clk_risc_BufferFalling

P#ArialArial%TX"*A*ALP23RL ArialP#Aririalc,,yMMHM,,,%TXQ^"*A*AQLP13%
(RL Arialr,HM(%MMM@MMm,BBBc
Percent 100

!


CORGROUP        $$clk_risc_BufferRisingFalling

Percent 100
H
!
c,,,,,,y,,,,,,,,,,,%c,,,,,88288782T8887!2%TXu"*A*AuLP12%
(RL Arial)@)GF)FF^F_F%TTFL"*A*AFLP0&%%V0i::i:i:%(%
(%
(%RL ArialGH@GHFH)Arial%Tw-*A*ALtPhysical Page Number             T.L=*A*A.     L`(22 bits)x&%%V0iU:i:U:Uii:%(RL Arial'xx
'#

P#ArialArial&" WMFC PPS%(%%T.*A*ALdPage Offset     
CORGROUP        $$clk_risc_BufferRising
T/>*A*A/     L`(13 bits)%
(RL ArialrialArialG@G%TX*A*ALP34RL Arial%(%TXO\*A*AOLP13%
(RL Arial%TXu*A*AuLP12%
(RL Arial%TTFL*A*AFLP0&%W$JJ%(%%V,&%%V&M&(-5@LZhv!.:CvJhMZMLJ@C5:-.(!&%(RL Arial%(%RL Arial%TA*A*AA
Percent 100
L`Page Table     T8*A*A8LdBase Address          T;.*A*A;Lddepending onTA/>*A*AA/Ldcurrent CID      &%%VX
!

%(%
(%RL Arial%TT*A*ALP+&%W(aaa%(%%V,&%%V0MMMM%(&%%V0MMMM%(%
(%RL Arial&ByValKt(CallGu*CasetL,CBool~Dirge?Dir$\@Do4ADoEventsDo
BDoubleuEachV;DElse%TT*A*ALP+f&%W,%(%%V,&%%W$JJ%(%%V,&%%W$JJ%(%%V,&%%V0::::%(     &rWMFCPPS&%%V0:6:66::6%(RL Arial !"#$%&'()*+,./01234%(%RL ArialFGHIJKLMNOPQRSTUVWXial,%TdY.x=*A*AY.LTPTE2   &     %     %V0:6:6:6:%(     %
(%RL Arial,,,,,,,,%c,,,,,
CORGROUP        $$clk_risc_BufferFalling
     
                         
Percent 100
      %T@*A*A@
LhL2 Page Table       & %     W,-**-*%(     %%V,,&:/,&:*,/,&& %     %W06***66%(     %%V,1::61:%RL      Arial     KK!!#8dd2!^KKB88888!J%8:!J7(7!!!:6C% T+q*A*A+qLVirtual Page Number  (VPN)                          &
!
%
W,IJIIJI[I[I%(
CORGROUP        $$clk_risc_BufferRisingFalling
%%V,ENNIEN&
Percent 100
%
!
%W,aiyayiyia%(
%
(RL Arial%(%
(%%T`*A*ALT255RL Arial%TT*A*ALP0%
(RL Arial%TT*A*ALP0%
(%
(RL Arial@?>=<:987543210/.-,+ri%Td*A*ALT2047<Y--$JJJ-.-
 Arial-2
CORGROUP        $$clk_risc_BufferRising
.+
Percent 100
Context ID          2
!
>5(4 bits)--$J}J}J--
 Arial?????????????????????????-"2
.Page Index Level 1      2
CORGROUP        $$clk_risc_BufferFalling
>(8 bits)--$}JiJi}}J--
 Arial?????????????????????????-"2
Percent 100
.Page Index Level 2      2
!
>    (11 bits)--$iJUJUiiJ--
 Arial?????????????????????????-2
.Page Offset    
CORGROUP        $$clk_risc_BufferRisingFalling
2
Percent 100
>    (13 bits)
 Arial??????????????????????-
!
2
35
 Arial?????????????????????????--
CORGROUP        $$clk_risc_BufferRising
2
Percent 100
31  "System cp#ρP-
 Arial?????????????????????????-
!
2
b24-
 Arial-
CORGROUP        $$clk_risc_BufferFalling
2
Percent 100
23
 ArialA???????-
!
2
Q13-
 Arial?U??o????ooo??Eoou???????-
CORGROUP        $$clk_risc_BufferRisingFalling
2
Percent 100
u12-
 Arial-  2
!
F0-
-$:i:i:-
CORGROUP        $$clk_risc_BufferRising
---
 Arial?@?-%2
Percent 100
Physical Page Number                  2
!
.    (22 bits)--$i:U:Uii:-
 Arial'xx
?---2
Page Offset    
CORGROUP        $$clk_risc_BufferFalling
2
Percent 100
/    (13 bits)-   
 Arial?????-
!
2
34
 Arial?????????????????????????-    -
CORGROUP        $$clk_risc_BufferRisingFalling
2
Percent 100
O13-
 Arial????????????????????????-
!
2
u12-
 Arial?????????????????????????-  2
CLOCK   clk_risc
F0-%J---$-
PERIODE 1
-:$&(-5@LZhv!.:CvJhMZMLJ@C5:-.(!&-
DUTY    50

 Arial?????????????????????????-
OFFSETE 0
-
 Arial?????????????????????????-2
INITIAL LOW
A
MAXUNCERTRISE   0
Page Table   2
MAXUNCERTFALL   0
8Base Address           2
MINUNCERTRISE   0
;depending on2
MINUNCERTFALL   0
/Acurrent CID         --"$
JRISEE  0

JFALLE  0
--- Arial???????????????-     2
GRID    1       1       1       2       2       16711680        0        0
+-
ENDGRID -1
%aa---$--$MMM---$MMM--       -
 Arial&???l???- 
2
DIRECTION       input
lPTE1         --$MMM-
 Arial?t???#H?????---!2
MASTERCLOCK     None
IL1 Page Directory               -%<<A---$@M@@--"$-- Arial?>~??r????????-    2
Clock   Unclocked
+-%---$--%J---$--%J---$--$:::---$:66::6-
 Arial--
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EdgeLevel       neg
.YPTE2         -
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-
 Arial?EEEE????????????????-
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2
ClockEnable     Not Used
@
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q+Virtual Page Number  (VPN)                                   -%IJI[I[I---$NIEN--%ayiyia--
 Arial?????????????????????????--       --2
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255
 Arial?????????????????????????-      2
ActiveLowClockEnable    True
0-
 Arial?????????????????????????-             2
VhdlType        std_logic
0--
 Arial?????????????????????????-
2
VerilogType     wire
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
US8@Td Arial@$N@Monotype Sorts@>NuWOingdR
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HighVoltageThreshold    5
J:DT1EW-hPT8*        
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NegTolerance    0
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PosTolerance    0
27(4M4]?
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VerilogCode
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E6      0        3000    3000            1       0        DR      0
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E7      0        3500    3500            1       0        DR      0
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E9      1       4500    4500            1       0        DR      0
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!
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SIGNAL  rst
BP(?d
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DIRECTION       input
`
RADIX   hex

GRID    0        1       0        1       0        16711680        0        0
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ENDGRID -1
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u
EdgeLevel       neg
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  E.#DB     u`h?\hr|uaU
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HighVoltageThreshold    5
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SignalActionType        0
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LSB     0
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isFallingEdgeSensitive  False
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SIGNAL  dbg_dat_o
/c/2/5Page Index Level 1
DIRECTION       output
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ActiveLowSetClear       True
Base Address
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HighVoltageThreshold    5
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LowVoltageThreshold     0
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LSB     0
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SignalActionType        0
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   True
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PosTolerance    0
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UserSpecifiedSizeRatio  1
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DIRECTION       input
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Clear   Not Used
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isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
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NegTolerance    0
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NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
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MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
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L`Context ID          
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}

 !"#$%&)*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`bcdefghijklmnopqrstuvwxyz{|}~  T|5>\MAA5>L\(4 bits)&%%V0}JJ}J}J%(%RL Arial%%T.<=AA.LpPage Index Level 1	T>XMAA>L|(VADDR_WIDTH-P1S-1 bits)                          
    &%%V0}iJ}JiJi}}J%(%RL Arial%T.(=AA.LpPage Index Level 2     T>MAA>Lh(P1S-P2S bits)        &%%V0iUJiJUJUiiJ%(%RL Arial%T.=AA.LdPage Offset 
CLOCKNAME       Unclocked
T>MAA>
CLOCKEDGE       neg
L`(P2S bits)  RL Arial%Tv"AA
LhVADDR_WIDTH-1                         
  RL Arial%T"AA
LhVADDR_WIDTH-1                         
  %
(%T`\t"AA\LTP1S      RL ArialB%Tl"AALXP1S-1      %
(%
(RL Arial%T`H`"AAHLTP2S  %
(RL Arial%Tlt"AAtLXP2S-1      RL Arial%TTFL"AAFLP0&%%V0i::i:i:%(%
(%
(%RL Arial%Tw-AALtPhysical Page Number               T.=AA.L|(PADDR_WIDTH-P2S-1 bits)                     
    &%%V0iU9i9U9Uii9%(%
(%RL Arial%T-AALdPage Offset 
IsApplyInput    False
T.=AA.
PROPS!
L`(P2S bits)  %
(RL Arial%TlAALdPADDR_WIDTH                     
  RL ArialiT"YYArialArialc,,yMMHM,,,,,,,,,,HHH,c%T`F^AAFLTP2SM  %
(RL Arial
!


PARM    Trh

MIN     NULL

MAX     NULL
H
COMMENT Reset Hold Time
c,,,,,,y,,,,,,,,,,,%c,,,,,
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
     %TltAAtLXP2S-1         %
(RL Arial       
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}

     
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
CLOCKNAME       Unclocked
CLOCKEDGE       neg



IsApplyInput    False
PROPS!
     
!

%TTFLAAFLP0     &%W$JJ%(%%V,&%%V&M&(-5@LZhv!.:CvJhMZMLJ@C5:-.(!&%(%
(RL Arial%(%RL Arial%TAAAA
SETUP   Trs
L`Page Table     T8AA8LdBase Address          T;.AA;Lddepending onTA/>AAA/Ldcurrent CID      &%%VX
FROM    clk_risc        E9      S0

TO      rst     E1      S1
%(%
(%RL Arial%TTAALP+&%W(aaa%(%%V,&%%V0MMMM%(&%%V0MMMM%(%
(%RL Arial   
                         
OUTARROWS       0
          
USERPLACED      0
DISPLAYAS       6
                
     %TdlAAlLTPTE1        &%%V0MMMM%(RL Arial                                
            
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
EnableHdlCodeGeneration False
OrderIndex      1
PROPS!

!
                                   %(%RL Arial%TSAAS
LhL1 Page Table       &%W,A<<A%(%%V,@M@M@@&%%VX%(%RL Arial,-./012345679:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghq%TTAALP+&        %     W,%(     %%V,& %     %W$JJ%( %%V,& %     %W$JJ%( %%V,&     %     %V0::::%(     &     %     %V0:6:66::6%(     %
(%RL ArialUVWXYZ\]^_`abcdefghijlmnopqr%TdY.x=AAY.LTPTE2  &     %     %V0:6:6:6:%(     RL      Arial%%     (%RL ArialUVVU-n000AB%T@AA@
LhL2 Page Table*     &
%
HOLD    Trh
W,-**-*%(
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%%V,,&:/,&:*,/,&&
TO      rst     E1      S1
%
OUTARROWS       0
%W06***66%(
USERPLACED      0
%%V,1::61:%RL
DISPLAYAS       6
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CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
T-qAA-qLVirtual Page Number (VPN)                      &%W,IJIIJI[I[I%(%%V,ENNIEN&%%W,aiyayiyia%(_PID_LINKBASE?       A
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
FMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.69q՜.+,D՜.+,FQ/    %8&" WMFCcR P3PSxU>FQ/ EMFPSXVISIODrawing
EnableHdlCodeGeneration False
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L`Context ID          T|5>\M*A*A5>L\(4 bits)&%%V0}JJ}J}J%(%RL Arial%T.<=*A*A.LpPage Index Level 1	T|>M*A*A>L\(8 bits)&%%V0}iJ}JiJi}}J%(%RL Arial%T.(=*A*A.LpPage Index Level 2  T> M*A*A>     L`(11 bits)&%%V0iUJiJUJUiiJ%(%RL Arial%T.=*A*A.LdPage Offset     
PROPS!
T>M*A*A>     L`(13 bits)RL Arial%TX"*A*ALP35RL Arial%(%TX"*A*ALP31%
(RL Arial%TXbo"*A*AbLP24%
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'#
!

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(RL Arialr,HM(%MMM@MMm,BBBc

MARKER  MARK0

ATTACH  rst     NULL    S1

TIME    2750.000000

RELATIVETIME    0.000000
H
DISPLAYAS       5
c,,,,,,y,,,,,,,,,,,%c,,,,,88288782T8887!2%TXu"*A*AuLP12%
(RL Arial)@)GF)FF^F_F%TTFL"*A*AFLP0&%%V0i::i:i:%(%
(%
(%RL ArialGH@GHFH)Arial%Tw-*A*ALtPhysical Page Number             T.L=*A*A.     L`(22 bits)x&%%V0iU:i:U:Uii:%(RL Arial'xx
'#
MARKERTYPE      Timebreak(Curved)

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WHILERETURN
T/>*A*A/     L`(13 bits)%
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REPEATNUMBER
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SNAPTO  0

COMPRESSTIME    0.000000
%(%
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COMMENT
     
                         
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BaseTimeUnit    1
!
DisplayTimeUnit 2
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CORGROUP        $$CLK_I_BufferFalling
TextGridY       6
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CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
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FromTime        0
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Percent 100
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CORGROUP        $$dwb_CLK_I_BufferRisingFalling
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Percent 100
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CORGROUP        $$dwb_CLK_I_BufferRising
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CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$iwb_CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$iwb_CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CLOCK   CLK_RISC
!
PERIODE 2.5
DUTY    50
CORGROUP        $$CLK_I_BufferRisingFalling
OFFSETE 0
Percent 100
INITIAL HIGH
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRising
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        2       0        16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       internal
MASTERCLOCK     None
CORGROUP        $$CLK_I_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_RISC_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CLOCK   iwb_CLK_I
!
PERIODE 5
DUTY    50
CORGROUP        $$CLK_RISC_BufferFalling
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_I_BufferRising
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_I_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
SIGNAL  iwb_ADR_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   True
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      V       -1      -1              1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      X       3125    3125            1       0        DR      0
Percent 100
E2      V       3126    3126    A0      1       0        DR      0
!
E3      X       3750    3750            1       0        DR      0
E4      V       13125   13125     A0    1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      X       13625   13625           1       0        DR      0
Percent 100
E6      V       23125   23125     A4    1       0        DR      0
!
E7      X       23625   23625           1       0        DR      0
E8      V       33125   33125     A8    1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E9      X       33625   33625           1       0        DR      0
Percent 100
E10     V       43125   43125     A12   1       0        DR      0
!
E11     X       43750   43750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
SIGNAL  iwb_DAT_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      X       11250   11250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      V       13125   13125   D0      1       0        DR      0
Percent 100
E2      X       21250   21250           1       0        DR      0
!
E3      V       23125   23125   D4      1       0        DR      0
E4      X       31250   31250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      V       33125   33125   D8      1       0        DR      0
Percent 100
E6      X       41250   41250           1       0        DR      0
!
E7      V       43125   43125   D12     1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  iwb_DAT_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  iwb_WE_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3125    3125            1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      1       3126    3126            1       0        DR      0
Percent 100
E2      0        13125   13125           1       0        DR      0
!
E3      X       13625   13625           1       0        DR      0
E4      0        23125   23125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E5      X       23625   23625           1       0        DR      0
Percent 100
E6      0        33125   33125           1       0        DR      0
!
E7      X       33625   33625           1       0        DR      0
E8      0        43125   43125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E9      X       43625   43625           1       0        DR      0
Percent 100
!
!
SIGNAL  iwb_SEL_O
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     3
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRising
E0      V       0        0           Valid        1       0        DR      0
Percent 100
E1      X       3750    3750            1       0        DR      0
!
E2      V       13125   13125       Valid       1       0        DR      0
E3      X       13625   13625           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E4      V       23125   23125     Valid 1       0        DR      0
Percent 100
E5      X       23625   23625           1       0        DR      0
!
E6      V       33125   33125     Valid 1       0        DR      0
E7      X       33625   33625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E8      V       43125   43125     Valid 1       0        DR      0
Percent 100
E9      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
SIGNAL  iwb_STB_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_I_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_I_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_RISC_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
E0      0        3750    3750            1       0        DR      0
!
E1      1       13125   13125           1       0        DR      0
E2      0        13625   13625           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRising
E3      1       23125   23125           1       0        DR      0
Percent 100
E4      0        23625   23625           1       0        DR      0
!
E5      1       33125   33125           1       0        DR      0
E6      0        33625   33625           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
E7      1       43125   43125           1       0        DR      0
Percent 100
E8      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
SIGNAL  iwb_ACK_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_RISC_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_I_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      0        11250   11250           1       0        DR      0
!
E1      1       13125   13125           1       0        DR      0
E2      0        21250   21250           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
E3      1       23125   23125           1       0        DR      0
Percent 100
E4      0        31250   31250           1       0        DR      0
!
E5      1       33125   33125           1       0        DR      0
E6      0        41250   41250           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRising
E7      1       43125   43125           1       0        DR      0
Percent 100
E8      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
SIGNAL  iwb_CYC_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_I_BufferRising
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_I_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRising
PROPS!
Percent 100
E0      0        3125    3125            1       0        DR      0
!
E1      1       43125   43125           1       0        DR      0
E2      0        43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  iwb_ERR_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$iwb_CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$iwb_CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CLOCK   CLK_RISC
HighVoltageThreshold    5
PERIODE 2.5
LowVoltageThreshold     0
DUTY    50
SignalActionType        0
OFFSETE 0
MSB     0
INITIAL HIGH
LSB     0
MAXUNCERTRISE   0
isFallingEdgeSensitive  False
MAXUNCERTFALL   0
isRisingEdgeSensitive   False
MINUNCERTRISE   0
DrawAnalog      0
MINUNCERTFALL   0
BooleanEquation
JRISEE  0
NegTolerance    0
JFALLE  0
PosTolerance    0
GRID    0        1       0        2       0        16711680        0        0
UserSpecifiedSizeRatio  1
ENDGRID -1
VerilogCode
DIRECTION       internal
VHDLCode
MASTERCLOCK     None
PROPS!
Clock   Unclocked
E0      0        43125   43125           1       0        DR      0
EdgeLevel       neg
E1      X       43750   43750           1       0        DR      0
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
SIGNAL  iwb_RTY_I
ActiveLowSetClear       True
DIRECTION       input
AsyncSetClear   True
RADIX   hex
ActiveLowClockEnable    True
GRID    0        1       0        1       0        16711680        0        0
VhdlType        std_logic
ENDGRID -1
VerilogType     wire
Clock   Unclocked
SystemCType     sc_logic
EdgeLevel       neg
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Set     Not Used
StateEquation   Hex(Inc(0,2,5))
Clear   Not Used
HighVoltageThreshold    5
ClockEnable     Not Used
LowVoltageThreshold     0
ActiveLowSetClear       True
MSB     0
AsyncSetClear   True
LSB     0
ActiveLowClockEnable    True
isFallingEdgeSensitive  False
VhdlType        std_logic
isRisingEdgeSensitive   False
VerilogType     wire
DrawAnalog      0
SystemCType     sc_logic
BooleanEquation
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
NegTolerance    0
StateEquation   Hex(Inc(0,2,5))
PosTolerance    0
HighVoltageThreshold    5
UserSpecifiedSizeRatio  1
LowVoltageThreshold     0
VerilogCode
SignalActionType        0
VHDLCode
MSB     0
PROPS!
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CLOCK   iwb_CLK_I
DrawAnalog      0
PERIODE 5
BooleanEquation
DUTY    50
NegTolerance    0
OFFSETE 0
PosTolerance    0
INITIAL LOW
UserSpecifiedSizeRatio  1
MAXUNCERTRISE   0
VerilogCode
MAXUNCERTFALL   0
VHDLCode
MINUNCERTRISE   0
PROPS!
MINUNCERTFALL   0
E0      0        43125   43125           1       0        DR      0
JRISEE  0
E1      X       43750   43750           1       0        DR      0
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
MARKER  MARK1
DIRECTION       input
ATTACH  iwb_SEL_O       NULL    S6
MASTERCLOCK     None
TIME    17500.000000
Clock   Unclocked
RELATIVETIME    0.000000
EdgeLevel       neg
DISPLAYAS       5
Set     Not Used
MARKERTYPE      Timebreak(Curved)
Clear   Not Used
WHILERETURN
ClockEnable     Not Used
REPEATNUMBER
ActiveLowSetClear       True
SNAPTO  0
AsyncSetClear   True
COMPRESSTIME    0.000000
ActiveLowClockEnable    True
COMMENT
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
MARKER  MARK2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ATTACH  iwb_STB_O       NULL    S7
StateEquation   Hex(Inc(0,2,5))
TIME    27500.000000
HighVoltageThreshold    5
RELATIVETIME    0.000000
LowVoltageThreshold     0
DISPLAYAS       5
MSB     0
MARKERTYPE      Timebreak(Curved)
LSB     0
WHILERETURN
isFallingEdgeSensitive  False
REPEATNUMBER
isRisingEdgeSensitive   True
SNAPTO  0
DrawAnalog      0
COMPRESSTIME    0.000000
BooleanEquation
COMMENT
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
MARKER  MARK3
VerilogCode
ATTACH  iwb_STB_O       NULL    S7
VHDLCode
TIME    37500.000000
PROPS!
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
SIGNAL  iwb_ADR_O
WHILERETURN
DIRECTION       output
REPEATNUMBER
RADIX   hex
SNAPTO  0
GRID    0        1       0        1       0        16711680        0        0
COMPRESSTIME    0.000000
ENDGRID -1
COMMENT
Clock
!
EdgeLevel       neg
Set     Not Used
MARKER  MARK0
Clear   Not Used
ATTACH  iwb_CLK_I       NULL    S1
ClockEnable     Not Used
TIME    7494.285714
ActiveLowSetClear       True
RELATIVETIME    0.000000
AsyncSetClear   True
DISPLAYAS       5
ActiveLowClockEnable    True
MARKERTYPE      Timebreak(Curved)
VhdlType        std_logic
WHILERETURN
VerilogType     wire
REPEATNUMBER
SystemCType     sc_logic
SNAPTO  0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
COMPRESSTIME    0.000000
StateEquation   Hex(Inc(0,2,5))
COMMENT
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
Timing Diagram Editor v7.1g - Output File
MSB     31
SignalActionType        0
PROJECT
isFallingEdgeSensitive  False
BaseTimeUnit    1
isRisingEdgeSensitive   True
DisplayTimeUnit 2
DrawAnalog      0
TextGridX       625.000000
BooleanEquation
TextGridY       6
NegTolerance    0
EdgeGridX       625.000000
PosTolerance    0
ImportStartTime 0.000000
UserSpecifiedSizeRatio  1
ImportEndTime   281474976710656.000000
VerilogCode
TimePerPixel    61.428571
VHDLCode
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
VhdlMapping     DefaultVhdlMapping
ColWidths       144,216,288,423,488
PROPS!
ScrollPos       0.000000,0.000000,0.000000
E0      V       -1      -1              1       0        DR      0
DefDelayRule    1
E1      X       3125    3125            1       0        DR      0
NoEventOverlap  NO
E2      V       3126    3126    A0      1       0        DR      0
SigLabelFontHeight      10
E3      X       3750    3750            1       0        DR      0
LabelHeight     12
E4      V       13125   13125     A0    1       0        DR      0
LoadLibsToMem   1
E5      X       13625   13625           1       0        DR      0
UseFullPathNames        1
E6      V       23125   23125     A4    1       0        DR      0
LibPath
E7      X       23625   23625           1       0        DR      0
EntireTime      YES
E8      V       33125   33125     A8    1       0        DR      0
PrintTimeSpecified      NO
E9      X       33625   33625           1       0        DR      0
FromTime        0
E10     V       43125   43125     A12   1       0        DR      0
ToTime  53.75
E11     X       43750   43750           1       0        DR      0
AllSignals      YES
!
CurrSelSigs     NO
PrintTo 2
SIGNAL  iwb_DAT_I
PrintFileName   C:\DOCS\wb_writeblock_typ.wmf
DIRECTION       input
PreviewInterchange      YES
RADIX   hex
PreviewTIFF5    NO
GRID    0        1       0        1       0        16711680        0        0
UseMargins      NO
ENDGRID -1
PrintTimeLine   NO
Clock
PrintBorderBox  YES
EdgeLevel       neg
PrintSigNames   YES
Set     Not Used
PrintSigNamesOnEachPage YES
Clear   Not Used
AddPreviewToEPS NO
ClockEnable     Not Used
PreviewRes      150
ActiveLowSetClear       True
MarginLR        1.25
AsyncSetClear   True
MifImageWidth   6.00
ActiveLowClockEnable    True
MarginTB        Auto
VhdlType        std_logic
Header  %d %t;%f;%p
VerilogType     wire
Footer
SystemCType     sc_logic
ScaleHorz       100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ScaleVert       100
StateEquation   Hex(Inc(0,2,5))
ScaleHPage      1
HighVoltageThreshold    5
PrintImage      DIAGRAM
LowVoltageThreshold     0
DefaultTimingModel      minmax
LSB     0
DefaultClock    Unclocked
MSB     31
DefaultEdgeLevel        neg
SignalActionType        0
DefaultSet      Not Used
isFallingEdgeSensitive  False
DefaultClear    Not Used
isRisingEdgeSensitive   False
DefaultClockEnable      Not Used
DrawAnalog      0
DefaultClockToOutLH     0
BooleanEquation
DefaultClockToOutHL     0
NegTolerance    0
DefaultSetup    0
PosTolerance    0
DefaultHold     0
UserSpecifiedSizeRatio  1
DefaultRegStartupState  unknown
VerilogCode
DefaultPodSize  8
VHDLCode
DefaultActiveLowSetClear        True
VhdlMapping     DefaultVhdlMapping
DefaultAsyncSetClear    True
PROPS!
DefaultActiveLowClockEnable     True
E0      X       11250   11250           1       0        DR      0
SigLabelFontHeight      10
E1      V       13125   13125   D0      1       0        DR      0
PROPS!
E2      X       21250   21250           1       0        DR      0
!
E3      V       23125   23125   D4      1       0        DR      0
E4      X       31250   31250           1       0        DR      0
STYLE
E5      V       33125   33125   D8      1       0        DR      0
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
E6      X       41250   41250           1       0        DR      0
DrawWndFont     DEFAULT
E7      V       43125   43125   D12     1       0        DR      0
DrawWndColor    DEFAULT
E8      X       43750   43750           1       0        DR      0
GridWndFont     DEFAULT
!
GridWndColor    DEFAULT
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
SIGNAL  iwb_DAT_O
LabelWndColor   DEFAULT
DIRECTION       output
ParamDispPref   0
RADIX   hex
ParamWndCellDisplay     0
GRID    0        1       0        1       0        16711680        0        0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
ENDGRID -1
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
Clock   Unclocked
MarkerDispPref  4
EdgeLevel       neg
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
Set     Not Used
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
Clear   Not Used
SignalColor     2
ClockEnable     Not Used
LabelOffset     2
ActiveLowSetClear       True
BusDisplay      0
AsyncSetClear   True
WaveFormWidth   0.500000
ActiveLowClockEnable    True
WaveFormColor   0
VhdlType        std_logic
InputWaveFormColor      16711680
VerilogType     wire
SlantedEdges    1
SystemCType     sc_logic
SlantAngle      75
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
RightJustifySigNames    1
StateEquation   Hex(Inc(0,2,5))
AutosplitEnabled        1
HighVoltageThreshold    5
AutosplitChar   _
LowVoltageThreshold     0
DynamSizedSignals       1
LSB     0
!
MSB     31
SignalActionType        0
DIAGRAMTESTBENCHSETTINGS
isFallingEdgeSensitive  False
FilesBeforeDiagramModel
isRisingEdgeSensitive   False
FilesInsideDiagramModelDeclarationSection
DrawAnalog      0
AbortHdlCodeEnabled     1
BooleanEquation
DelayHdlCodeEnabled     1
NegTolerance    0
SampleHdlCodeEnabled    1
PosTolerance    0
MarkerHdlCodeEnabled    1
UserSpecifiedSizeRatio  1
VerboseSamples  0
VerilogCode
VerboseDelays   0
VHDLCode
VerboseFileInput        0
PROPS!
VerboseSequenceVerification     0
E0      X       43750   43750           1       0        DR      0
IncludeDelayTime        1
!
ExecuteFromTopLevel     1
TimeOutInDiagramLengths 0
SIGNAL  iwb_WE_O
DefaultCycleClock       Unclocked
DIRECTION       output
DefaultCycleEdge        neg
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
MACROS
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferRising
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      X       3125    3125            1       0        DR      0
!
E1      1       3126    3126            1       0        DR      0
E2      0        13125   13125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E3      X       13625   13625           1       0        DR      0
Percent 100
E4      0        23125   23125           1       0        DR      0
!
E5      X       23625   23625           1       0        DR      0
E6      0        33125   33125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E7      X       33625   33625           1       0        DR      0
Percent 100
E8      0        43125   43125           1       0        DR      0
!
E9      X       43625   43625           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  iwb_SEL_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     3
SignalActionType        0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      V       0        0           Valid        1       0        DR      0
E1      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E2      V       13125   13125       Valid       1       0        DR      0
Percent 100
E3      X       13625   13625           1       0        DR      0
!
E4      V       23125   23125     Valid 1       0        DR      0
E5      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E6      V       33125   33125     Valid 1       0        DR      0
Percent 100
E7      X       33625   33625           1       0        DR      0
!
E8      V       43125   43125     Valid 1       0        DR      0
E9      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  iwb_STB_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        13625   13625           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        33625   33625           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  iwb_ACK_I
DIRECTION       input
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        11250   11250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        21250   21250           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        31250   31250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        41250   41250           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
SIGNAL  iwb_CYC_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3125    3125            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E1      1       43125   43125           1       0        DR      0
Percent 100
E2      0        43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferFalling
SIGNAL  iwb_ERR_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_RISC_BufferRisingFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRising
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      0        43125   43125           1       0        DR      0
!
E1      X       43750   43750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
SIGNAL  iwb_RTY_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_I_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRising
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      0        43125   43125           1       0        DR      0
E1      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
MARKER  MARK1
ATTACH  iwb_SEL_O       NULL    S6
CORGROUP        $$CLK_RISC_BufferRisingFalling
TIME    17500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_I_BufferRising
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_I_BufferFalling
COMMENT
Percent 100
!
!
MARKER  MARK2
CORGROUP        $$CLK_I_BufferRisingFalling
ATTACH  iwb_STB_O       NULL    S7
Percent 100
TIME    27500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_RISC_BufferRising
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_RISC_BufferFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
MARKER  MARK3
Percent 100
ATTACH  iwb_STB_O       NULL    S7
!
TIME    37500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_I_BufferRising
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_I_BufferFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
MARKER  MARK0
!
ATTACH  iwb_CLK_I       NULL    S1
TIME    7494.285714
CORGROUP        $$CLK_RISC_BufferRising
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_RISC_BufferFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
Timing Diagram Editor v7.1g - Output File
CORGROUP        $$CLK_I_BufferRising
PROJECT
Percent 100
BaseTimeUnit    1
!
DisplayTimeUnit 2
TextGridX       625.000000
CORGROUP        $$CLK_I_BufferFalling
TextGridY       6
Percent 100
EdgeGridX       625.000000
!
ImportStartTime 0.000000
ImportEndTime   281474976710656.000000
CORGROUP        $$CLK_I_BufferRisingFalling
TimePerPixel    61.428571
Percent 100
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
!
ColWidths       144,216,288,423,488
ScrollPos       0.000000,0.000000,0.000000
CORGROUP        $$dwb_CLK_RISC_BufferRising
DefDelayRule    1
Percent 100
NoEventOverlap  NO
!
SigLabelFontHeight      10
LabelHeight     12
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LoadLibsToMem   1
Percent 100
UseFullPathNames        1
!
LibPath
EntireTime      YES
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
PrintTimeSpecified      NO
Percent 100
FromTime        0
!
ToTime  53.75
AllSignals      YES
CORGROUP        $$dwb_CLK_I_BufferRising
CurrSelSigs     NO
Percent 100
PrintTo 2
!
PrintFileName   C:\DOCS\wb_writeblock_typ.wmf
PreviewInterchange      YES
CORGROUP        $$dwb_CLK_I_BufferFalling
PreviewTIFF5    NO
Percent 100
UseMargins      NO
!
PrintTimeLine   NO
PrintBorderBox  YES
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
PrintSigNames   YES
Percent 100
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
CORGROUP        $$dwb_CLK_RISC_BufferRising
MarginLR        1.25
Percent 100
MifImageWidth   6.00
!
MarginTB        Auto
Header  %d %t;%f;%p
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Footer
Percent 100
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
PrintImage      DIAGRAM
Percent 100
DefaultTimingModel      minmax
!
DefaultClock    Unclocked
DefaultEdgeLevel        neg
CORGROUP        $$dwb_CLK_I_BufferRising
DefaultSet      Not Used
Percent 100
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
CORGROUP        $$dwb_CLK_I_BufferFalling
DefaultClockToOutHL     0
Percent 100
DefaultSetup    0
!
DefaultHold     0
DefaultRegStartupState  unknown
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DefaultPodSize  8
Percent 100
DefaultActiveLowSetClear        True
!
DefaultAsyncSetClear    True
DefaultActiveLowClockEnable     True
CORGROUP        $$dwb_CLK_RISC_BufferRising
SigLabelFontHeight      10
Percent 100
PROPS!
!
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
STYLE
Percent 100
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
GridWndFont     DEFAULT
Percent 100
GridWndColor    DEFAULT
!
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
LabelWndColor   DEFAULT
CORGROUP        $$dwb_CLK_I_BufferRising
ParamDispPref   0
Percent 100
ParamWndCellDisplay     0
!
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
CORGROUP        $$dwb_CLK_I_BufferFalling
MarkerDispPref  4
Percent 100
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
SignalColor     2
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
LabelOffset     2
Percent 100
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
CORGROUP        $$dwb_CLK_RISC_BufferRising
InputWaveFormColor      16711680
Percent 100
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
AutosplitEnabled        1
Percent 100
AutosplitChar   _
!
DynamSizedSignals       1
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
DIAGRAMTESTBENCHSETTINGS
!
FilesBeforeDiagramModel
FilesInsideDiagramModelDeclarationSection
CORGROUP        $$dwb_CLK_I_BufferRising
AbortHdlCodeEnabled     1
Percent 100
DelayHdlCodeEnabled     1
!
SampleHdlCodeEnabled    1
MarkerHdlCodeEnabled    1
CORGROUP        $$dwb_CLK_I_BufferFalling
VerboseSamples  0
Percent 100
VerboseDelays   0
!
VerboseFileInput        0
VerboseSequenceVerification     0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
IncludeDelayTime        1
Percent 100
ExecuteFromTopLevel     1
!
TimeOutInDiagramLengths 0
DefaultCycleClock       Unclocked
CORGROUP        $$dwb_CLK_RISC_BufferRising
DefaultCycleEdge        neg
Percent 100
!
!
MACROS
CORGROUP        $$dwb_CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$dwb_CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$dwb_CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CLOCK   CLK_RISC
!
PERIODE 2.5
DUTY    50
CORGROUP        $$CLK_I_BufferRisingFalling
OFFSETE 0
Percent 100
INITIAL HIGH
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRising
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        2       0        16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       internal
MASTERCLOCK     None
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_I_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CLOCK   dwb_CLK_I
!
PERIODE 5
DUTY    50
CORGROUP        $$CLK_RISC_BufferFalling
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_I_BufferRising
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_I_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
SIGNAL  dwb_ADR_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   True
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      V       -1      -1              1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      X       3123    3123            1       0        DR      0
Percent 100
E2      V       13125   13125     A0    1       0        DR      0
!
E3      X       13625   13625           1       0        DR      0
E4      V       23125   23125     A4    1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      X       23625   23625           1       0        DR      0
Percent 100
E6      V       33125   33125     A8    1       0        DR      0
!
E7      X       33625   33625           1       0        DR      0
E8      V       43125   43125     A12   1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E9      X       43750   43750           1       0        DR      0
Percent 100
E10     V       53125   53125    A0     1       0        DR      0
!
E11     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
SIGNAL  dwb_DAT_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      X       11250   11250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      V       13125   13125   D0      1       0        DR      0
Percent 100
E2      X       21250   21250           1       0        DR      0
!
E3      V       23125   23125   D4      1       0        DR      0
E4      X       31250   31250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      V       33125   33125   D8      1       0        DR      0
Percent 100
E6      X       41250   41250           1       0        DR      0
!
E7      V       43125   43125   D12     1       0        DR      0
E8      X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dwb_DAT_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3125    3125            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E1      V       3126    3126    D0      1       0        DR      0
Percent 100
E2      X       43125   43125           1       0        DR      0
!
E3      V       53124   53124     D0    1       0        DR      0
E4      X       53750   53750           1       
CORGROUP        $$CLK_RISC_BufferRisingFalling

O !"#$%&'()*+,-./012345789:;<=>?@ABCDEFGHIJKLMNQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  0        DR      0
Percent 100
!
!
SIGNAL  dwb_WE_O
CORGROUP        $$CLK_I_BufferRising
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRisingFalling
E0      X       3126    3126            1       0        DR      0
Percent 100
E1      0        13125   13125           1       0        DR      0
!
E2      X       13625   13625           1       0        DR      0
E3      0        23125   23125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E4      X       23625   23625           1       0        DR      0
Percent 100
E5      0        33125   33125           1       0        DR      0
!
E6      X       33750   33750           1       0        DR      0
E7      0        43125   43125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E8      1       53125   53125           1       0        DR      0
Percent 100
E9      0        53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
SIGNAL  dwb_SEL_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_RISC_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LSB     0
Percent 100
MSB     3
!
SignalActionType        0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_I_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_I_BufferFalling
PROPS!
Percent 100
E0      X       3123    3123            1       0        DR      0
!
E1      V       13125   13125       Valid       1       0        DR      0
E2      X       13625   13625           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
E3      V       23125   23125     Valid 1       0        DR      0
Percent 100
E4      X       23625   23625           1       0        DR      0
!
E5      V       33125   33125     Valid 1       0        DR      0
E6      X       33625   33625           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
E7      V       43125   43125     Valid 1       0        DR      0
Percent 100
E8      X       43750   43750           1       0        DR      0
!
E9      V       53124   53124      Valid        1       0        DR      0
E10     X       53750   53750           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  dwb_STB_O
DIRECTION       output
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$dwb_CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$dwb_CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$dwb_CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$dwb_CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3750    3750            1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        13625   13625           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        23625   23625           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        33625   33625           1       0        DR      0
!
E7      1       43124   43124           1       0        DR      0
E8      0        44466   44466           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
E9      1       53124   53124           1       0        DR      0
Percent 100
E10     X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
SIGNAL  dwb_ACK_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_I_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_I_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_RISC_BufferRising
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_RISC_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_I_BufferRising
PROPS!
Percent 100
E0      0        11250   11250           1       0        DR      0
!
E1      1       13125   13125           1       0        DR      0
E2      0        21250   21250           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
E3      1       23125   23125           1       0        DR      0
Percent 100
E4      0        31250   31250           1       0        DR      0
!
E5      1       33125   33125           1       0        DR      0
E6      0        41250   41250           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
E7      1       43124   43124           1       0        DR      0
Percent 100
E8      0        51875   51875           1       0        DR      0
!
E9      1       53124   53124           1       0        DR      0
E10     X       53750   53750           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
!
Percent 100
!
SIGNAL  dwb_CYC_O
DIRECTION       output
CORGROUP        $$dwb_CLK_RISC_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$dwb_CLK_I_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$dwb_CLK_I_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3125    3125            1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRising
E1      1       43125   43125           1       0        DR      0
Percent 100
E2      0        44375   44375           1       0        DR      0
!
E3      1       53125   53125           1       0        DR      0
E4      0        53750   53750           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dwb_ERR_I
DIRECTION       input
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CLOCK   CLK_RISC
EdgeLevel       neg
PERIODE 2.5
Set     Not Used
DUTY    50
Clear   Not Used
OFFSETE 0
ClockEnable     Not Used
INITIAL HIGH
ActiveLowSetClear       True
MAXUNCERTRISE   0
AsyncSetClear   True
MAXUNCERTFALL   0
ActiveLowClockEnable    True
MINUNCERTRISE   0
VhdlType        std_logic
MINUNCERTFALL   0
VerilogType     wire
JRISEE  0
SystemCType     sc_logic
JFALLE  0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
GRID    0        1       0        2       0        16711680        0        0
StateEquation   Hex(Inc(0,2,5))
ENDGRID -1
HighVoltageThreshold    5
DIRECTION       internal
LowVoltageThreshold     0
MASTERCLOCK     None
SignalActionType        0
Clock   Unclocked
MSB     0
EdgeLevel       neg
LSB     0
Set     Not Used
isFallingEdgeSensitive  False
Clear   Not Used
isRisingEdgeSensitive   False
ClockEnable     Not Used
DrawAnalog      0
ActiveLowSetClear       True
BooleanEquation
AsyncSetClear   True
NegTolerance    0
ActiveLowClockEnable    True
PosTolerance    0
VhdlType        std_logic
UserSpecifiedSizeRatio  1
VerilogType     wire
VerilogCode
SystemCType     sc_logic
VHDLCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PROPS!
StateEquation   Hex(Inc(0,2,5))
E0      0        53125   53125           1       0        DR      0
HighVoltageThreshold    5
E1      X       53750   53750           1       0        DR      0
LowVoltageThreshold     0
!
MSB     0
LSB     0
SIGNAL  dwb_RTY_I
isFallingEdgeSensitive  False
DIRECTION       input
isRisingEdgeSensitive   False
RADIX   hex
DrawAnalog      0
GRID    0        1       0        1       0        16711680        0        0
BooleanEquation
ENDGRID -1
NegTolerance    0
Clock   Unclocked
PosTolerance    0
EdgeLevel       neg
UserSpecifiedSizeRatio  1
Set     Not Used
VerilogCode
Clear   Not Used
VHDLCode
ClockEnable     Not Used
PROPS!
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CLOCK   dwb_CLK_I
VhdlType        std_logic
PERIODE 5
VerilogType     wire
DUTY    50
SystemCType     sc_logic
OFFSETE 0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
INITIAL LOW
StateEquation   Hex(Inc(0,2,5))
MAXUNCERTRISE   0
HighVoltageThreshold    5
MAXUNCERTFALL   0
LowVoltageThreshold     0
MINUNCERTRISE   0
SignalActionType        0
MINUNCERTFALL   0
MSB     0
JRISEE  0
LSB     0
JFALLE  0
isFallingEdgeSensitive  False
GRID    1       1       1       2       2       16711680        0        0
isRisingEdgeSensitive   False
ENDGRID -1
DrawAnalog      0
DIRECTION       input
BooleanEquation
MASTERCLOCK     None
NegTolerance    0
Clock   Unclocked
PosTolerance    0
EdgeLevel       neg
UserSpecifiedSizeRatio  1
Set     Not Used
VerilogCode
Clear   Not Used
VHDLCode
ClockEnable     Not Used
PROPS!
ActiveLowSetClear       True
E0      0        53125   53125           1       0        DR      0
AsyncSetClear   True
E1      X       53750   53750           1       0        DR      0
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
MARKER  MARK1
SystemCType     sc_logic
ATTACH  dwb_SEL_O       NULL    S6
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
TIME    17500.000000
StateEquation   Hex(Inc(0,2,5))
RELATIVETIME    0.000000
HighVoltageThreshold    5
DISPLAYAS       5
LowVoltageThreshold     0
MARKERTYPE      Timebreak(Curved)
MSB     0
WHILERETURN
LSB     0
REPEATNUMBER
isFallingEdgeSensitive  False
SNAPTO  0
isRisingEdgeSensitive   True
COMPRESSTIME    0.000000
DrawAnalog      0
COMMENT
BooleanEquation
!
NegTolerance    0
PosTolerance    0
MARKER  MARK2
UserSpecifiedSizeRatio  1
ATTACH  dwb_STB_O       NULL    S7
VerilogCode
TIME    27500.000000
VHDLCode
RELATIVETIME    0.000000
PROPS!
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
SIGNAL  dwb_ADR_O
REPEATNUMBER
DIRECTION       output
SNAPTO  0
RADIX   hex
COMPRESSTIME    0.000000
GRID    0        1       0        1       0        16711680        0        0
COMMENT
ENDGRID -1
!
Clock
EdgeLevel       neg
MARKER  MARK3
Set     Not Used
ATTACH  dwb_STB_O       NULL    S7
Clear   Not Used
TIME    37500.000000
ClockEnable     Not Used
RELATIVETIME    0.000000
ActiveLowSetClear       True
DISPLAYAS       5
AsyncSetClear   True
MARKERTYPE      Timebreak(Curved)
ActiveLowClockEnable    True
WHILERETURN
VhdlType        std_logic
REPEATNUMBER
VerilogType     wire
SNAPTO  0
SystemCType     sc_logic
COMPRESSTIME    0.000000
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
COMMENT
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
MARKER  MARK0
LSB     0
ATTACH  dwb_CLK_I       NULL    S1
MSB     31
TIME    7500.000000
SignalActionType        0
RELATIVETIME    0.000000
isFallingEdgeSensitive  False
DISPLAYAS       5
isRisingEdgeSensitive   True
MARKERTYPE      Timebreak(Curved)
DrawAnalog      0
WHILERETURN
BooleanEquation
REPEATNUMBER
NegTolerance    0
SNAPTO  0
PosTolerance    0
COMPRESSTIME    0.000000
UserSpecifiedSizeRatio  1
COMMENT
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
MARKER  MARK4
PROPS!
ATTACH  dwb_ADR_O       NULL    S2
E0      V       -1      -1              1       0        DR      0
TIME    47500.000000
E1      X       3123    3123            1       0        DR      0
RELATIVETIME    0.000000
E2      V       13125   13125     A0    1       0        DR      0
DISPLAYAS       5
E3      X       13625   13625           1       0        DR      0
MARKERTYPE      Timebreak(Curved)
E4      V       23125   23125     A4    1       0        DR      0
WHILERETURN
E5      X       23625   23625           1       0        DR      0
REPEATNUMBER
E6      V       33125   33125     A8    1       0        DR      0
SNAPTO  0
E7      X       33625   33625           1       0        DR      0
COMPRESSTIME    0.000000
E8      V       43125   43125     A12   1       0        DR      0
COMMENT
E9      X       43750   43750           1       0        DR      0
!
E10     V       53125   53125    A0     1       0        DR      0
E11     X       53750   53750           1       0        DR      0

!
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
SIGNAL  dwb_DAT_I
DIRECTION       input
PROJECT
RADIX   hex
BaseTimeUnit    1
GRID    0        1       0        1       0        16711680        0        0
DisplayTimeUnit 2
ENDGRID -1
TextGridX       625.000000
Clock
TextGridY       6
EdgeLevel       neg
EdgeGridX       625.000000
Set     Not Used
ImportStartTime 0.000000
Clear   Not Used
ImportEndTime   281474976710656.000000
ClockEnable     Not Used
TimePerPixel    50.000000
ActiveLowSetClear       True
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
AsyncSetClear   True
ColWidths       144,216,288,423,488
ActiveLowClockEnable    True
ScrollPos       0.000000,0.000000,0.000000
VhdlType        std_logic
DefDelayRule    1
VerilogType     wire
NoEventOverlap  NO
SystemCType     sc_logic
SigLabelFontHeight      10
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LabelHeight     12
StateEquation   Hex(Inc(0,2,5))
LoadLibsToMem   1
HighVoltageThreshold    5
UseFullPathNames        1
LowVoltageThreshold     0
LibPath
LSB     0
EntireTime      YES
MSB     31
PrintTimeSpecified      NO
SignalActionType        0
FromTime        0
isFallingEdgeSensitive  False
ToTime  43.75
isRisingEdgeSensitive   False
AllSignals      YES
DrawAnalog      0
CurrSelSigs     NO
BooleanEquation
PrintTo 2
NegTolerance    0
PrintFileName   C:\DOCS\wb_readblock_typ.wmf
PosTolerance    0
PreviewInterchange      YES
UserSpecifiedSizeRatio  1
PreviewTIFF5    NO
VerilogCode
UseMargins      NO
VHDLCode
PrintTimeLine   NO
VhdlMapping     DefaultVhdlMapping
PrintBorderBox  YES
PROPS!
PrintSigNames   YES
E0      X       11250   11250           1       0        DR      0
PrintSigNamesOnEachPage YES
E1      V       13125   13125   D0      1       0        DR      0
AddPreviewToEPS NO
E2      X       21250   21250           1       0        DR      0
PreviewRes      150
E3      V       23125   23125   D4      1       0        DR      0
MarginLR        1.25
E4      X       31250   31250           1       0        DR      0
MifImageWidth   6.00
E5      V       33125   33125   D8      1       0        DR      0
MarginTB        Auto
E6      X       41250   41250           1       0        DR      0
Header  %d %t;%f;%p
E7      V       43125   43125   D12     1       0        DR      0
Footer
E8      X       53750   53750           1       0        DR      0
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
SIGNAL  dwb_DAT_O
PrintImage      DIAGRAM
DIRECTION       output
DefaultTimingModel      minmax
RADIX   hex
DefaultClock    Unclocked
GRID    0        1       0        1       0        16711680        0        0
DefaultEdgeLevel        neg
ENDGRID -1
DefaultSet      Not Used
Clock   Unclocked
DefaultClear    Not Used
EdgeLevel       neg
DefaultClockEnable      Not Used
Set     Not Used
DefaultClockToOutLH     0
Clear   Not Used
DefaultClockToOutHL     0
ClockEnable     Not Used
DefaultSetup    0
ActiveLowSetClear       True
DefaultHold     0
AsyncSetClear   True
DefaultRegStartupState  unknown
ActiveLowClockEnable    True
DefaultPodSize  8
VhdlType        std_logic
DefaultActiveLowSetClear        True
VerilogType     wire
DefaultAsyncSetClear    True
SystemCType     sc_logic
DefaultActiveLowClockEnable     True
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SigLabelFontHeight      10
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
STYLE
MSB     31
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
SignalActionType        0
DrawWndFont     DEFAULT
isFallingEdgeSensitive  False
DrawWndColor    DEFAULT
isRisingEdgeSensitive   False
GridWndFont     DEFAULT
DrawAnalog      0
GridWndColor    DEFAULT
BooleanEquation
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
NegTolerance    0
LabelWndColor   DEFAULT
PosTolerance    0
ParamDispPref   0
UserSpecifiedSizeRatio  1
ParamWndCellDisplay     0
VerilogCode
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
VHDLCode
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
PROPS!
MarkerDispPref  4
E0      X       3125    3125            1       0        DR      0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
E1      V       3126    3126    D0      1       0        DR      0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
E2      X       43125   43125           1       0        DR      0
SignalColor     2
E3      V       53124   53124     D0    1       0        DR      0
LabelOffset     2
E4      X       53750   53750           1       0        DR      0
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
SIGNAL  dwb_WE_O
InputWaveFormColor      16711680
DIRECTION       output
SlantedEdges    1
RADIX   hex
SlantAngle      75
GRID    0        1       0        1       0        16711680        0        0
RightJustifySigNames    1
ENDGRID -1
AutosplitEnabled        1
Clock   Unclocked
AutosplitChar   _
EdgeLevel       neg
DynamSizedSignals       1
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
DIAGRAMTESTBENCHSETTINGS
ActiveLowSetClear       True
FilesBeforeDiagramModel
AsyncSetClear   True
FilesInsideDiagramModelDeclarationSection
ActiveLowClockEnable    True
AbortHdlCodeEnabled     1
VhdlType        std_logic
DelayHdlCodeEnabled     1
VerilogType     wire
SampleHdlCodeEnabled    1
SystemCType     sc_logic
MarkerHdlCodeEnabled    1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerboseSamples  0
StateEquation   Hex(Inc(0,2,5))
VerboseDelays   0
HighVoltageThreshold    5
VerboseFileInput        0
LowVoltageThreshold     0
VerboseSequenceVerification     0
SignalActionType        0
IncludeDelayTime        1
MSB     0
ExecuteFromTopLevel     1
LSB     0
TimeOutInDiagramLengths 0
isFallingEdgeSensitive  False
DefaultCycleClock       Unclocked
isRisingEdgeSensitive   False
DefaultCycleEdge        neg
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
MACROS
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      X       3126    3126            1       0        DR      0
E1      0        13125   13125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E2      X       13625   13625           1       0        DR      0
Percent 100
E3      0        23125   23125           1       0        DR      0
!
E4      X       23625   23625           1       0        DR      0
E5      0        33125   33125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E6      X       33750   33750           1       0        DR      0
Percent 100
E7      0        43125   43125           1       0        DR      0
!
E8      1       53125   53125           1       0        DR      0
E9      0        53750   53750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
SIGNAL  dwb_SEL_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     3
CORGROUP        $$CLK_I_BufferRising
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3123    3123            1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E1      V       13125   13125       Valid       1       0        DR      0
Percent 100
E2      X       13625   13625           1       0        DR      0
!
E3      V       23125   23125     Valid 1       0        DR      0
E4      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E5      V       33125   33125     Valid 1       0        DR      0
Percent 100
E6      X       33625   33625           1       0        DR      0
!
E7      V       43125   43125     Valid 1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E9      V       53124   53124      Valid        1       0        DR      0
Percent 100
E10     X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_STB_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
E0      0        3750    3750            1       0        DR      0
!
E1      1       13125   13125           1       0        DR      0
E2      0        13625   13625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E3      1       23125   23125           1       0        DR      0
Percent 100
E4      0        23625   23625           1       0        DR      0
!
E5      1       33125   33125           1       0        DR      0
E6      0        33625   33625           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E7      1       43124   43124           1       0        DR      0
Percent 100
E8      0        44466   44466           1       0        DR      0
!
E9      1       53124   53124           1       0        DR      0
E10     X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_ACK_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        11250   11250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        21250   21250           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        31250   31250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        41250   41250           1       0        DR      0
!
E7      1       43124   43124           1       0        DR      0
E8      0        51875   51875           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E9      1       53124   53124           1       0        DR      0
Percent 100
E10     X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
SIGNAL  dwb_CYC_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_RISC_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      0        3125    3125            1       0        DR      0
!
E1      1       43125   43125           1       0        DR      0
E2      0        44375   44375           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E3      1       53125   53125           1       0        DR      0
Percent 100
E4      0        53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_ERR_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      0        53125   53125           1       0        DR      0
!
E1      X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
SIGNAL  dwb_RTY_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        53125   53125           1       0        DR      0
E1      X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
MARKER  MARK1
ATTACH  dwb_SEL_O       NULL    S6
CORGROUP        $$CLK_I_BufferFalling
TIME    17500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_I_BufferRisingFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_RISC_BufferRising
COMMENT
Percent 100
!
!
MARKER  MARK2
CORGROUP        $$CLK_RISC_BufferFalling
ATTACH  dwb_STB_O       NULL    S7
Percent 100
TIME    27500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_RISC_BufferRisingFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_I_BufferRising
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_I_BufferFalling
MARKER  MARK3
Percent 100
ATTACH  dwb_STB_O       NULL    S7
!
TIME    37500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_I_BufferRisingFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_RISC_BufferRising
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
MARKER  MARK0
!
ATTACH  dwb_CLK_I       NULL    S1
TIME    7500.000000
CORGROUP        $$CLK_RISC_BufferRisingFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_I_BufferRising
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
MARKER  MARK4
ATTACH  dwb_ADR_O       NULL    S2
CORGROUP        $$CLK_I_BufferRisingFalling
TIME    47500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_RISC_BufferRising
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_RISC_BufferFalling
COMMENT
Percent 100
!
!

CORGROUP        $$CLK_RISC_BufferRisingFalling
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
Percent 100
FMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.69qTiming Diagram Editor v7.1g - Output File
!
PROJECT
CORGROUP        $$CLK_I_BufferRising
BaseTimeUnit    1
Percent 100
DisplayTimeUnit 2
!
TextGridX       250.000000
TextGridY       6
CORGROUP        $$CLK_I_BufferFalling
EdgeGridX       250.000000
Percent 100
ImportStartTime 0.000000
!
ImportEndTime   281474976710656.000000
TimePerPixel    6.497175
CORGROUP        $$CLK_I_BufferRisingFalling
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
Percent 100
ColWidths       144,216,288,423,488
!
ScrollPos       0.000000,0.000000,0.000000
DefDelayRule    1
CORGROUP        $$dwb_CLK_RISC_BufferRising
NoEventOverlap  NO
Percent 100
SigLabelFontHeight      10
!
LabelHeight     12
LoadLibsToMem   1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
UseFullPathNames        1
Percent 100
LibPath
!
EntireTime      YES
PrintTimeSpecified      NO
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
FromTime        0
Percent 100
ToTime  5.75
!
AllSignals      YES
CurrSelSigs     NO
CORGROUP        $$dwb_CLK_I_BufferRising
PrintTo 2
Percent 100
PrintFileName   C:\DOCS\reset_gated.wmf
!
PreviewInterchange      YES
PreviewTIFF5    NO
CORGROUP        $$dwb_CLK_I_BufferFalling
UseMargins      NO
Percent 100
PrintTimeLine   NO
!
PrintBorderBox  YES
PrintSigNames   YES
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
PrintSigNamesOnEachPage YES
Percent 100
AddPreviewToEPS NO
!
PreviewRes      150
MarginLR        1.25
CORGROUP        $$dwb_CLK_RISC_BufferRising
MifImageWidth   6.00
Percent 100
MarginTB        Auto
!
Header  %d %t;%f;%p
Footer
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ScaleHorz       100
Percent 100
ScaleVert       100
!
ScaleHPage      1
PrintImage      DIAGRAM
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
DefaultTimingModel      minmax
Percent 100
DefaultClock    Unclocked
!
DefaultEdgeLevel        neg
DefaultSet      Not Used
CORGROUP        $$dwb_CLK_I_BufferRising
DefaultClear    Not Used
Percent 100
DefaultClockEnable      Not Used
!
DefaultClockToOutLH     0
DefaultClockToOutHL     0
CORGROUP        $$dwb_CLK_I_BufferFalling
DefaultSetup    0
Percent 100
DefaultHold     0
!
DefaultRegStartupState  unknown
DefaultPodSize  8
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DefaultActiveLowSetClear        True
Percent 100
DefaultAsyncSetClear    True
!
DefaultActiveLowClockEnable     True
SigLabelFontHeight      10
CORGROUP        $$dwb_CLK_RISC_BufferRising
PROPS!
Percent 100
!
!
STYLE
CORGROUP        $$dwb_CLK_RISC_BufferFalling
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
Percent 100
DrawWndFont     DEFAULT
!
DrawWndColor    DEFAULT
GridWndFont     DEFAULT
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
GridWndColor    DEFAULT
Percent 100
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
!
LabelWndColor   DEFAULT
ParamDispPref   0
CORGROUP        $$dwb_CLK_I_BufferRising
ParamWndCellDisplay     0
Percent 100
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
!
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
MarkerDispPref  4
CORGROUP        $$dwb_CLK_I_BufferFalling
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
Percent 100
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
!
SignalColor     2
LabelOffset     4
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
BusDisplay      0
Percent 100
WaveFormWidth   0.500000
!
WaveFormColor   0
InputWaveFormColor      16711680
CORGROUP        $$dwb_CLK_RISC_BufferRising
SlantedEdges    1
Percent 100
SlantAngle      75
!
RightJustifySigNames    1
AutosplitEnabled        1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
AutosplitChar   _
Percent 100
DynamSizedSignals       1
!
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
DIAGRAMTESTBENCHSETTINGS
Percent 100
FilesBeforeDiagramModel
!
FilesInsideDiagramModelDeclarationSection
AbortHdlCodeEnabled     1
CORGROUP        $$dwb_CLK_I_BufferRising
DelayHdlCodeEnabled     1
Percent 100
SampleHdlCodeEnabled    1
!
MarkerHdlCodeEnabled    1
VerboseSamples  0
CORGROUP        $$dwb_CLK_I_BufferFalling
VerboseDelays   0
Percent 100
VerboseFileInput        0
!
VerboseSequenceVerification     0
IncludeDelayTime        1
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
ExecuteFromTopLevel     1
Percent 100
TimeOutInDiagramLengths 0
!
DefaultCycleClock       Unclocked
DefaultCycleEdge        neg
CORGROUP        $$dwb_CLK_RISC_BufferRising
!
Percent 100
!
MACROS
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CLOCK   CLK_RISC
PERIODE 2.5
CORGROUP        $$CLK_I_BufferRisingFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL HIGH
MAXUNCERTRISE   0
CORGROUP        $$CLK_I_BufferRising
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_I_BufferFalling
JFALLE  0
Percent 100
GRID    0        1       0        2       0        16711680        0        0
!
ENDGRID -1
DIRECTION       internal
CORGROUP        $$CLK_I_BufferRisingFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CLOCK   dwb_CLK_I
PERIODE 5
CORGROUP        $$CLK_RISC_BufferFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL LOW
MAXUNCERTRISE   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_I_BufferRising
JFALLE  0
Percent 100
GRID    1       1       1       2       2       16711680        0        0
!
ENDGRID -1
DIRECTION       input
CORGROUP        $$CLK_I_BufferFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_I_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_ADR_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_I_BufferRisingFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      V       -1      -1              1       0        DR      0
Percent 100
E1      X       3125    3125            1       0        DR      0
!
E2      V       3126    3126    A0      1       0        DR      0
E3      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E4      V       13125   13125     A0    1       0        DR      0
Percent 100
E5      X       13625   13625           1       0        DR      0
!
E6      V       23125   23125     A4    1       0        DR      0
E7      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E8      V       33125   33125     A8    1       0        DR      0
Percent 100
E9      X       33625   33625           1       0        DR      0
!
E10     V       43125   43125     A12   1       0        DR      0
E11     X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_DAT_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      X       11250   11250           1       0        DR      0
Percent 100
E1      V       13125   13125   D0      1       0        DR      0
!
E2      X       21250   21250           1       0        DR      0
E3      V       23125   23125   D4      1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E4      X       31250   31250           1       0        DR      0
Percent 100
E5      V       33125   33125   D8      1       0        DR      0
!
E6      X       41250   41250           1       0        DR      0
E7      V       43125   43125   D12     1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E8      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_DAT_O
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferFalling
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_WE_O
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$clk_risc_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$clk_risc_BufferFalling
E0      X       3125    3125            1       0        DR      0
Percent 100
E1      1       3126    3126            1       0        DR      0
!
E2      0        13125   13125           1       0        DR      0
E3      X       13625   13625           1       0        DR      0
CORGROUP        $$clk_risc_BufferRisingFalling
E4      0        23125   23125           1       0        DR      0
Percent 100
E5      X       23625   23625           1       0        DR      0
!
E6      0        33125   33125           1       0        DR      0
E7      X       33625   33625           1       0        DR      0
CORGROUP        $$clk_risc_BufferRising
E8      0        43125   43125           1       0        DR      0
Percent 100
E9      X       43625   43625           1       0        DR      0
!
!
CORGROUP        $$clk_risc_BufferFalling
SIGNAL  dwb_SEL_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$clk_risc_BufferRisingFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$clk_risc_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$clk_risc_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$clk_risc_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$clk_risc_BufferRising
LSB     0
Percent 100
MSB     3
!
SignalActionType        0
isFallingEdgeSensitive  False
CORGROUP        $$clk_risc_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$clk_risc_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$clk_risc_BufferRising
PROPS!
Percent 100
E0      V       0        0           Valid        1       0        DR      0
!
E1      X       3750    3750            1       0        DR      0
E2      V       13125   13125       Valid       1       0        DR      0
CORGROUP        $$clk_risc_BufferFalling
E3      X       13625   13625           1       0        DR      0
Percent 100
E4      V       23125   23125     Valid 1       0        DR      0
!
E5      X       23625   23625           1       0        DR      0
E6      V       33125   33125     Valid 1       0        DR      0
CORGROUP        $$clk_risc_BufferRisingFalling
E7      X       33625   33625           1       0        DR      0
Percent 100
E8      V       43125   43125     Valid 1       0        DR      0
!
E9      X       43750   43750           1       0        DR      0
!
CORGROUP        $$clk_risc_BufferRising
Percent 100
SIGNAL  dwb_STB_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$clk_risc_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$clk_risc_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CLOCK   clk_risc
AsyncSetClear   True
PERIODE 1
ActiveLowClockEnable    True
DUTY    50
VhdlType        std_logic
OFFSETE 4.5
VerilogType     wire
INITIAL HIGH
SystemCType     sc_logic
MAXUNCERTRISE   0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MAXUNCERTFALL   0
StateEquation   Hex(Inc(0,2,5))
MINUNCERTRISE   0
HighVoltageThreshold    5
MINUNCERTFALL   0
LowVoltageThreshold     0
JRISEE  0
SignalActionType        0
JFALLE  0
MSB     0
GRID    1       1       0        2       2       16711680        0        0
LSB     0
ENDGRID -1
isFallingEdgeSensitive  False
DIRECTION       input
isRisingEdgeSensitive   False
MASTERCLOCK     None
DrawAnalog      0
Clock   Unclocked
BooleanEquation
EdgeLevel       neg
NegTolerance    0
Set     Not Used
PosTolerance    0
Clear   Not Used
UserSpecifiedSizeRatio  1
ClockEnable     Not Used
VerilogCode
ActiveLowSetClear       True
VHDLCode
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
E0      0        3750    3750            1       0        DR      0
VhdlType        std_logic
E1      1       13125   13125           1       0        DR      0
VerilogType     wire
E2      0        13625   13625           1       0        DR      0
SystemCType     sc_logic
E3      1       23125   23125           1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E4      0        23625   23625           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E5      1       33125   33125           1       0        DR      0
HighVoltageThreshold    5
E6      0        33625   33625           1       0        DR      0
LowVoltageThreshold     0
E7      1       43125   43125           1       0        DR      0
MSB     0
E8      X       43750   43750           1       0        DR      0
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
SIGNAL  dwb_ACK_I
DrawAnalog      0
DIRECTION       input
BooleanEquation
RADIX   hex
NegTolerance    0
GRID    0        1       0        1       0        16711680        0        0
PosTolerance    0
ENDGRID -1
UserSpecifiedSizeRatio  1
Clock   Unclocked
VerilogCode
EdgeLevel       neg
VHDLCode
Set     Not Used
PROPS!
Clear   Not Used
E5      1       7000    7000            1       0        DR      0
ClockEnable     Not Used
E6      0        7500    7500            1       0        DR      0
ActiveLowSetClear       True
E7      1       8000    8000            1       0        DR      0
AsyncSetClear   True
E9      1       9000    9000            1       0        DR      0
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
SIGNAL  rst
SystemCType     sc_logic
DIRECTION       input
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
RADIX   hex
StateEquation   Hex(Inc(0,2,5))
GRID    0        1       0        1       0        16711680        0        0
HighVoltageThreshold    5
ENDGRID -1
LowVoltageThreshold     0
Clock   Unclocked
SignalActionType        0
EdgeLevel       neg
MSB     0
Set     Not Used
LSB     0
Clear   Not Used
isFallingEdgeSensitive  False
ClockEnable     Not Used
isRisingEdgeSensitive   False
ActiveLowSetClear       True
DrawAnalog      0
AsyncSetClear   True
BooleanEquation
ActiveLowClockEnable    True
NegTolerance    0
VhdlType        std_logic
PosTolerance    0
VerilogType     wire
UserSpecifiedSizeRatio  1
SystemCType     sc_logic
VerilogCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VHDLCode
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
E0      0        11250   11250           1       0        DR      0
LowVoltageThreshold     0
E1      1       13125   13125           1       0        DR      0
SignalActionType        0
E2      0        21250   21250           1       0        DR      0
MSB     0
E3      1       23125   23125           1       0        DR      0
LSB     0
E4      0        31250   31250           1       0        DR      0
isFallingEdgeSensitive  False
E5      1       33125   33125           1       0        DR      0
isRisingEdgeSensitive   False
E6      0        41250   41250           1       0        DR      0
DrawAnalog      0
E7      1       43125   43125           1       0        DR      0
BooleanEquation
E8      X       43750   43750           1       0        DR      0
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
SIGNAL  dwb_CYC_O
VerilogCode
DIRECTION       output
VHDLCode
RADIX   hex
PROPS!
GRID    0        1       0        1       0        16711680        0        0
E0      0        1750    1750            1       0        DR      0
ENDGRID -1
E1      1       3750    3750            1       0        DR      0
Clock   Unclocked
E2      0        5750    5750            1       0        DR      0
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
SIGNAL  dbg_dat_o
ClockEnable     Not Used
DIRECTION       output
ActiveLowSetClear       True
RADIX   hex
AsyncSetClear   True
GRID    0        1       0        1       0        16711680        0        0
ActiveLowClockEnable    True
ENDGRID -1
VhdlType        std_logic
Clock
VerilogType     wire
EdgeLevel       neg
SystemCType     sc_logic
Set     Not Used
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Clear   Not Used
StateEquation   Hex(Inc(0,2,5))
ClockEnable     Not Used
HighVoltageThreshold    5
ActiveLowSetClear       True
LowVoltageThreshold     0
AsyncSetClear   True
SignalActionType        0
ActiveLowClockEnable    True
MSB     0
VhdlType        std_logic
LSB     0
VerilogType     wire
isFallingEdgeSensitive  False
SystemCType     sc_logic
isRisingEdgeSensitive   False
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DrawAnalog      0
StateEquation   Hex(Inc(0,2,5))
BooleanEquation
HighVoltageThreshold    5
NegTolerance    0
LowVoltageThreshold     0
PosTolerance    0
LSB     0
UserSpecifiedSizeRatio  1
MSB     31
VerilogCode
SignalActionType        0
VHDLCode
isFallingEdgeSensitive  False
PROPS!
isRisingEdgeSensitive   True
E0      0        3125    3125            1       0        DR      0
DrawAnalog      0
E1      1       43125   43125           1       0        DR      0
BooleanEquation
E2      0        43750   43750           1       0        DR      0
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
SIGNAL  dwb_ERR_I
VerilogCode
DIRECTION       input
VHDLCode
RADIX   hex
VhdlMapping     DefaultVhdlMapping
GRID    0        1       0        1       0        16711680        0        0
PROPS!
ENDGRID -1
E0      X       1750    1750            1       0        DR      0
Clock   Unclocked
E1      V       4750    4750    0x0     1       0        DR      0
EdgeLevel       neg
E2      V       5750    5750    0x4     1       0        DR      0
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
SIGNAL  dbg_op_i
ActiveLowSetClear       True
DIRECTION       input
AsyncSetClear   True
RADIX   hex
ActiveLowClockEnable    True
GRID    0        1       0        1       0        16711680        0        0
VhdlType        std_logic
ENDGRID -1
VerilogType     wire
Clock   Unclocked
SystemCType     sc_logic
EdgeLevel       neg
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Set     Not Used
StateEquation   Hex(Inc(0,2,5))
Clear   Not Used
HighVoltageThreshold    5
ClockEnable     Not Used
LowVoltageThreshold     0
ActiveLowSetClear       True
SignalActionType        0
AsyncSetClear   True
MSB     0
ActiveLowClockEnable    True
LSB     0
VhdlType        std_logic
isFallingEdgeSensitive  False
VerilogType     wire
isRisingEdgeSensitive   False
SystemCType     sc_logic
DrawAnalog      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
BooleanEquation
StateEquation   Hex(Inc(0,2,5))
NegTolerance    0
HighVoltageThreshold    5
PosTolerance    0
LowVoltageThreshold     0
UserSpecifiedSizeRatio  1
SignalActionType        0
VerilogCode
MSB     3
VHDLCode
LSB     0
PROPS!
isFallingEdgeSensitive  False
E0      0        43125   43125           1       0        DR      0
isRisingEdgeSensitive   False
E1      X       43750   43750           1       0        DR      0
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
SIGNAL  dwb_RTY_I
PosTolerance    0
DIRECTION       input
UserSpecifiedSizeRatio  1
RADIX   hex
VerilogCode
GRID    0        1       0        1       0        16711680        0        0
VHDLCode
ENDGRID -1
PROPS!
Clock   Unclocked
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
MARKER  MARK0
ClockEnable     Not Used
ATTACH  rst     NULL    S1
ActiveLowSetClear       True
TIME    2750.000000
AsyncSetClear   True
RELATIVETIME    0.000000
ActiveLowClockEnable    True
DISPLAYAS       5
VhdlType        std_logic
MARKERTYPE      Timebreak(Curved)
VerilogType     wire
WHILERETURN
SystemCType     sc_logic
REPEATNUMBER
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SNAPTO  0
StateEquation   Hex(Inc(0,2,5))
COMPRESSTIME    0.000000
HighVoltageThreshold    5
COMMENT
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
FQ/     %8&" WMFCcR P3PSxU>FQ/ EMFPSXVISIODrawing
LSB     0
 Y=&%%V0JJJJ%(%RL Arialdx		_VarMemberFlagsVB_Var@?>=<;:98%T+.g=*A*A+.
isFallingEdgeSensitive  False
L`Context ID          T|5>\M*A*A5>L\(4 bits)&%%V0}JJ}J}J%(%RL Arial%T.<=*A*A.LpPage Index Level 1	T|>M*A*A>L\(8 bits)&%%V0}iJ}JiJi}}J%(%RL Arial%T.(=*A*A.LpPage Index Level 2  T> M*A*A>     L`(11 bits)&%%V0iUJiJUJUiiJ%(%RL Arial%T.=*A*A.LdPage Offset     
isRisingEdgeSensitive   False
T>M*A*A>     L`(13 bits)RL Arial%TX"*A*ALP35RL Arial%(%TX"*A*ALP31%
(RL Arial%TXbo"*A*AbLP24%
(RL Arial'xx
'#
DrawAnalog      0

P#ArialArial%TX"*A*ALP23RL ArialP#Aririalc,,yMMHM,,,%TXQ^"*A*AQLP13%
(RL Arialr,HM(%MMM@MMm,BBBc
BooleanEquation

NegTolerance    0

PosTolerance    0

UserSpecifiedSizeRatio  1

VerilogCode
H
VHDLCode
c,,,,,,y,,,,,,,,,,,%c,,,,,88288782T8887!2%TXu"*A*AuLP12%
(RL Arial)@)GF)FF^F_F%TTFL"*A*AFLP0&%%V0i::i:i:%(%
(%
(%RL ArialGH@GHFH)Arial%Tw-*A*ALtPhysical Page Number             T.L=*A*A.     L`(22 bits)x&%%V0iU:i:U:Uii:%(RL Arial'xx
'#
PROPS!

P#ArialArial&" WMFC PPS%(%%T.*A*ALdPage Offset     
E0      0        43125   43125           1       0        DR      0
T/>*A*A/     L`(13 bits)%
(RL ArialrialArialG@G%TX*A*ALP34RL Arial%(%TXO\*A*AOLP13%
(RL Arial%TXu*A*AuLP12%
(RL Arial%TTFL*A*AFLP0&%W$JJ%(%%V,&%%V&M&(-5@LZhv!.:CvJhMZMLJ@C5:-.(!&%(RL Arial%(%RL Arial%TA*A*AA
E1      X       43750   43750           1       0        DR      0
L`Page Table     T8*A*A8LdBase Address          T;.*A*A;Lddepending onTA/>*A*AA/Ldcurrent CID      &%%VX
!

%(%
(%RL Arial%TT*A*ALP+&%W(aaa%(%%V,&%%V0MMMM%(&%%V0MMMM%(%
(%RL Arial&ByValKt(CallGu*CasetL,CBool~Dirge?Dir$\@Do4ADoEventsDo
BDoubleuEachV;DElse%TT*A*ALP+f&%W,%(%%V,&%%W$JJ%(%%V,&%%W$JJ%(%%V,&%%V0::::%(     &rWMFCPPS&%%V0:6:66::6%(RL Arial !"#$%&'()*+,./01234%(%RL ArialFGHIJKLMNOPQRSTUVWXial,%TdY.x=*A*AY.LTPTE2   &     %     %V0:6:6:6:%(     %
(%RL Arial,,,,,,,,%c,,,,,
MARKER  MARK1
     
                         
ATTACH  dwb_SEL_O       NULL    S6
      %T@*A*A@
LhL2 Page Table       & %     W,-**-*%(     %%V,,&:/,&:*,/,&& %     %W06***66%(     %%V,1::61:%RL      Arial     KK!!#8dd2!^KKB88888!J%8:!J7(7!!!:6C% T+q*A*A+qLVirtual Page Number  (VPN)                          &
TIME    17500.000000
%
RELATIVETIME    0.000000
W,IJIIJI[I[I%(
DISPLAYAS       5
%%V,ENNIEN&
MARKERTYPE      Timebreak(Curved)
%
WHILERETURN
%W,aiyayiyia%(
REPEATNUMBER
%
(RL Arial%(%
(%%T`*A*ALT255RL Arial%TT*A*ALP0%
(RL Arial%TT*A*ALP0%
(%
(RL Arial@?>=<:987543210/.-,+ri%Td*A*ALT2047<Y--$JJJ-.-
 Arial-2
SNAPTO  0
.+
COMPRESSTIME    0.000000
Context ID          2
COMMENT
>5(4 bits)--$J}J}J--
 Arial?????????????????????????-"2
!
.Page Index Level 1      2
>(8 bits)--$}JiJi}}J--
 Arial?????????????????????????-"2
MARKER  MARK2
.Page Index Level 2      2
ATTACH  dwb_STB_O       NULL    S7
>    (11 bits)--$iJUJUiiJ--
 Arial?????????????????????????-2
TIME    27500.000000
.Page Offset    
RELATIVETIME    0.000000
2
DISPLAYAS       5
>    (13 bits)
 Arial??????????????????????-
MARKERTYPE      Timebreak(Curved)
2
WHILERETURN
35
 Arial?????????????????????????--
REPEATNUMBER
2
SNAPTO  0
31  "System cp#ρP-
 Arial?????????????????????????-
COMPRESSTIME    0.000000
2
COMMENT
b24-
 Arial-
!
2
23
 ArialA???????-
MARKER  MARK3
2
ATTACH  dwb_STB_O       NULL    S7
Q13-
 Arial?U??o????ooo??Eoou???????-
TIME    37500.000000
2
RELATIVETIME    0.000000
u12-
 Arial-  2
DISPLAYAS       5
F0-
MARKERTYPE      Timebreak(Curved)
-$:i:i:-
WHILERETURN
---
 Arial?@?-%2
REPEATNUMBER
Physical Page Number                  2
SNAPTO  0
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!
                
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CORGROUP        $$CLK_RISC_BufferRising
Percent 100
!

CORGROUP        $$CLK_RISC_BufferFalling
                                   %(%RL Arial%TSAAS
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CORGROUP        $$CLK_RISC_BufferRising
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Percent 100
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!
FMicrosoft Visio DrawingVISITiming Diagram Editor v7.1g - Output File
CORGROUP        $$CLK_RISC_BufferFalling
PROJECT
Percent 100
BaseTimeUnit    1
!
DisplayTimeUnit 2
TextGridX       625.000000
CORGROUP        $$CLK_RISC_BufferRisingFalling
TextGridY       6
Percent 100
EdgeGridX       625.000000
!
ImportStartTime 0.000000
ImportEndTime   281474976710656.000000
CORGROUP        $$CLK_I_BufferRising
TimePerPixel    50.000000
Percent 100
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
!
ColWidths       144,216,288,423,488
ScrollPos       0.000000,0.000000,0.000000
CORGROUP        $$CLK_I_BufferFalling
DefDelayRule    1
Percent 100
NoEventOverlap  NO
!
SigLabelFontHeight      10
LabelHeight     12
CORGROUP        $$CLK_I_BufferRisingFalling
LoadLibsToMem   1
Percent 100
UseFullPathNames        1
!
LibPath
EntireTime      YES
CORGROUP        $$CLK_RISC_BufferRising
PrintTimeSpecified      NO
Percent 100
FromTime        0
!
ToTime  43.75
AllSignals      YES
CORGROUP        $$CLK_RISC_BufferFalling
CurrSelSigs     NO
Percent 100
PrintTo 2
!
PrintFileName   C:\DOCS\wb_readblock_typ.wmf
PreviewInterchange      YES
CORGROUP        $$CLK_RISC_BufferRisingFalling
PreviewTIFF5    NO
Percent 100
UseMargins      NO
!
PrintTimeLine   NO
PrintBorderBox  YES
CORGROUP        $$CLK_I_BufferRising
PrintSigNames   YES
Percent 100
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
CORGROUP        $$CLK_I_BufferFalling
MarginLR        1.25
Percent 100
MifImageWidth   6.00
!
MarginTB        Auto
Header  %d %t;%f;%p
CORGROUP        $$CLK_I_BufferRisingFalling
Footer
Percent 100
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
CORGROUP        $$CLK_RISC_BufferRising
PrintImage      DIAGRAM
Percent 100
DefaultTimingModel      minmax
!
DefaultClock    Unclocked
DefaultEdgeLevel        neg
CORGROUP        $$CLK_RISC_BufferFalling
DefaultSet      Not Used
Percent 100
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
DefaultClockToOutHL     0
Percent 100
DefaultSetup    0
!
DefaultHold     0
DefaultRegStartupState  unknown
CORGROUP        $$CLK_I_BufferRising
DefaultPodSize  8
Percent 100
DefaultActiveLowSetClear        True
!
DefaultAsyncSetClear    True
DefaultActiveLowClockEnable     True
CORGROUP        $$CLK_I_BufferFalling
SigLabelFontHeight      10
Percent 100
PROPS!
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
STYLE
Percent 100
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
CORGROUP        $$CLK_RISC_BufferRising
GridWndFont     DEFAULT
Percent 100
GridWndColor    DEFAULT
!
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
LabelWndColor   DEFAULT
CORGROUP        $$CLK_RISC_BufferFalling
ParamDispPref   0
Percent 100
ParamWndCellDisplay     0
!
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
CORGROUP        $$CLK_RISC_BufferRisingFalling
MarkerDispPref  4
Percent 100
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
SignalColor     2
CORGROUP        $$CLK_RISC_BufferRising
LabelOffset     2
Percent 100
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
CORGROUP        $$CLK_RISC_BufferFalling
InputWaveFormColor      16711680
Percent 100
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
AutosplitEnabled        1
Percent 100
AutosplitChar   _
!
DynamSizedSignals       1
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
DIAGRAMTESTBENCHSETTINGS
!
FilesBeforeDiagramModel
FilesInsideDiagramModelDeclarationSection
CORGROUP        $$CLK_RISC_BufferFalling
AbortHdlCodeEnabled     1
Percent 100
DelayHdlCodeEnabled     1
!
SampleHdlCodeEnabled    1
MarkerHdlCodeEnabled    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerboseSamples  0
Percent 100
VerboseDelays   0
!
VerboseFileInput        0
VerboseSequenceVerification     0
CORGROUP        $$CLK_RISC_BufferRising
IncludeDelayTime        1
Percent 100
ExecuteFromTopLevel     1
!
TimeOutInDiagramLengths 0
DefaultCycleClock       Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
DefaultCycleEdge        neg
Percent 100
!
!
MACROS
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CLOCK   clk_risc
!
PERIODE 1
DUTY    50
CORGROUP        $$CLK_I_BufferFalling
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRisingFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_RISC_BufferRising
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E5      1       2500    2500            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E6      0        3000    3000            1       0        DR      0
Percent 100
E7      0        3500    3500            1       0        DR      0
!
E9      1       4500    4500            1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  rst
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        1750    1750            1       0        DR      0
E1      1       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E2      0        5750    5750            1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_dat_o
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      X       1750    1750            1       0        DR      0
!
E1      V       4750    4750    0x0     1       0        DR      0
E2      V       5750    5750    0x4     1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dbg_op_i
DIRECTION       input
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     3
CORGROUP        $$CLK_I_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
PARM    Trs
MIN     NULL
CORGROUP        $$CLK_RISC_BufferRisingFalling
MAX     NULL
Percent 100
COMMENT Reset Setup Time
!
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
CORGROUP        $$CLK_I_BufferRising
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
Percent 100
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
!
CLOCKNAME       Unclocked
CLOCKEDGE       neg
CORGROUP        $$CLK_I_BufferFalling
IsApplyInput    False
Percent 100
PROPS!
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
PARM    Trh
Percent 100
MIN     NULL
!
MAX     NULL
COMMENT Reset Hold Time
CORGROUP        $$CLK_RISC_BufferRising
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
Percent 100
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
!
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
CORGROUP        $$CLK_RISC_BufferFalling
CLOCKNAME       Unclocked
Percent 100
CLOCKEDGE       neg
!
IsApplyInput    False
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SETUP   Trs
FROM    clk_risc        E9      S0
CORGROUP        $$CLK_I_BufferRising
TO      rst     E1      S1
Percent 100
OUTARROWS       0
!
USERPLACED      0
DISPLAYAS       6
CORGROUP        $$CLK_I_BufferFalling
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Percent 100
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
EnableHdlCodeGeneration False
OrderIndex      1
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
!
!
HOLD    Trh
CORGROUP        $$dwb_CLK_RISC_BufferRising
FROM    clk_risc        E7      S0
Percent 100
TO      rst     E1      S1
!
OUTARROWS       0
USERPLACED      0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
DISPLAYAS       6
Percent 100
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
!
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
EnableHdlCodeGeneration False
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
OrderIndex      2
Percent 100
PROPS!
!
!
CORGROUP        $$dwb_CLK_I_BufferRising
MARKER  MARK0
Percent 100
ATTACH  rst     NULL    S1
!
TIME    2750.000000
RELATIVETIME    0.000000
CORGROUP        $$dwb_CLK_I_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100

!
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CORGROUP        $$dwb_CLK_I_BufferRising
@= 
LTSETIC--)RL Arialts use by you is covered under the terms of a liceagreement. You have obtained this typeface software either directly from Monotype or together with software distributed by onef Monotypes licensees.
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!
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If you have any questconcerning your rights you should review the license agreement you received with the software or contact Monotype for a copy othe license agreement.
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Monotype can be contacted at:
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%(RL ArialL0MMLNpNNNNOPQQR*RSSTTTWXlXY"Z@ZZZ[[[[[\]]^B^_`Vaabbcde&fRfgXghizjkkm mooo%(RL ArialH:x2
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!
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@LXINDEX00-+&%W$
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@LP31%%RL Arial&" WMFC yp
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@LTlogRL Arial()*+,-/0123456789:;<=?@ABCDE%TT
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LowVoltageThreshold     0
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MSB     0
@QLLXFAULT)-0%)T?
LSB     0
@
isFallingEdgeSensitive  False
@     L`EXCEPTION-+0--)40&%W(%(%%V9
isRisingEdgeSensitive   True



DrawAnalog      0
.-C Arial???????-2
BooleanEquation
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NegTolerance    0
!SET 1--)%C Arial?????????????????????????-2
PosTolerance    0
       b...C Arial?????????????????????????-2
UserSpecifiedSizeRatio  1
        
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[VPN 0--0%2
SIGNAL  dwb_ADR_O
VPN 1--0%C Arial???????????????????????-  2
DIRECTION       output
       ...C Arial????????c????????????????-
RADIX   hex
-2
GRID    0        1       0        1       0        16711680        0        0
,
VPN!!$2
ENDGRID -1
h
ITLB_SETS-1!!!!--$kL L     kkL--C Arial?????????????????????????-!2
Clock
EFFECTIVE ADDRESS-))-0(---000-----$G
5       
5     GG
-C Arial?????????????????????????-C Arial?????????????????????????-C Arial?????????????-C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-        C Arial?A?A?A?A?A?A?A?A?A?A?A?A?- 
EdgeLevel       neg
C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-
Set     Not Used
C Arial?A?A?A?A?A?A?A?A?A?A?A?A?---C Arial?A?A?A?A?A?A?A?AA?A?A?A?-2
Clear   Not Used
o]PPN 0--0%2
ClockEnable     Not Used
]PPN 1--0%-2
ActiveLowSetClear       True
       ...C Arial????????????????????????p-2
AsyncSetClear   True
PPN ITLB_SETS-2--0)%-%--)-%2
ActiveLowClockEnable    True
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PPN ITLB_SETS-1--0)%-%--)-%---$ LL          L---        --$LLL--
VhdlType        std_logic
--%L-----%Y
Y
---%BLB
VerilogType     wire
---$%%-C Arial-2
SystemCType     sc_logic
kTLB SET)%---)2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
INDEX00-+-%
StateEquation   Hex(Inc(0,2,5))
X
HighVoltageThreshold    5
---$N       
LowVoltageThreshold     0
N=
LSB     0
N     -  -$-     --
2
MSB     31
XCOMP047--      %h- --$^}^^- -%
h- --$B^^B^- -$-     ---2
SignalActionType        0
'INV0--%``7---$.`9..C
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
 Arial----2
DrawAnalog      0
HIT 00)%-C Arial-
BooleanEquation
2
NegTolerance    0
31%%2 Arial-2
PosTolerance    0
log! Arial()*+,--               2
UserSpecifiedSizeRatio  1
22 Arial?????????????????????????-
VerilogCode
-
VHDLCode
2
VhdlMapping     DefaultVhdlMapping
(ITLB_SETS)+13!!!!-C Arial?????????????????????????-
PROPS!
2
E0      V       -1      -1              1       0        DR      0
I13%%-  2
E1      X       3125    3125            1       0        DR      0
0%S Arial?????????????5???????????-2
E2      V       3126    3126    A0      1       0        DR      0
WAY 0O98.-%---$-C
E3      X       3750    3750            1       0        DR      0
E4      V       13125   13125     A0    1       0        DR      0
 ArialialRegularMonotype:Arial -2
E5      X       13625   13625           1       0        DR      0
    ITLB MISS)%-7--2
E6      V       23125   23125     A4    1       0        DR      0
l    EXCEPTION-+0--)40--   C Arialy of its predecessors and-
E7      X       23625   23625           1       0        DR      0
2
E8      V       33125   33125     A8    1       0        DR      0
12%%-    %- --$- -%- - -%
- - -%- --v$9       
E9      X       33625   33625           1       0        DR      0

E10     V       43125   43125     A12   1       0        DR      0
     -       -%- --$-
E11     X       43750   43750           1       0        DR      0
--C
!
 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
SIGNAL  dwb_DAT_I
jPADDR[31:13]--000%%%%-
DIRECTION       input
%L>-       - -%>*- --$!!     !C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-     -- 2
RADIX   hex
~PAGE OFFSET--4-4))--)2
GRID    0        1       0        1       0        16711680        0        0
FPADDR[12:0]--000%%%-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-! Arial????????????????????????--2 Arial????????????????????c????-2
ENDGRID -1
Clock
log! Arial?????????????????????????-  2
EdgeLevel       neg
Q
Set     Not Used
22 Arial????????????????????????-
Clear   Not Used
2
ClockEnable     Not Used
c
ActiveLowSetClear       True
(ITLB_SETS)+12!!!!-%---$zb
b
zz-C Arial?????????????-2
AsyncSetClear   True
D & A attributes0--%%%%"--$a
ActiveLowClockEnable    True
eea
VhdlType        std_logic
a
VerilogType     wire
e--        -C Arial?A?A?A?A?A?A?A?A?A?A?A?A?- 2
SystemCType     sc_logic

TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
PAGE FAULT--4-)-0%)-%       9    9---$     a
HighVoltageThreshold    5
9     `     --%      9     ----$mMMmmM-C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
LowVoltageThreshold     0
vSR[SUPV-0-0--  2
LSB     0
4]-%        ---$     a
MSB     31
          --%          ------$}      }}C Arial?????????????????????????-
SignalActionType        0
-C Arial?????????????????????????-2
isFallingEdgeSensitive  False
BACCESS-00---
2
isRisingEdgeSensitive   False
TYPE)----%%
---$.
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--      --2
DrawAnalog      0
Hz
BooleanEquation
PROTECTION-04)-0)402
NegTolerance    0

PosTolerance    0
ATTRIBUTES-))0-0)---%e---$fC
UserSpecifiedSizeRatio  1
VerilogCode
 Arial?#???C???--C
VHDLCode
VhdlMapping     DefaultVhdlMapping
 ArialE-???AC?A??-2
PROPS!
    DMMU PAGE0770--4-2
E0      X       11250   11250           1       0        DR      0
LQFAULT)-0%)2
E1      V       13125   13125   D0      1       0        DR      0
    EXCEPTION-+0--)40-
E2      X       21250   21250           1       0        DR      0
%-       --v$9
E3      V       23125   23125   D4      1       0        DR      0



E4      X       31250   31250           1       0        DR      0
Visio (TM) Drawing
E5      V       33125   33125   D8      1       0        DR      0
NTH2MRl !fffMMM333$
E6      X       41250   41250           1       0        DR      0
$
E7      V       43125   43125   D12     1       0        DR      0
U38@Td Arial@NWingdzs@N@tMonotype Sort+
NtSymbol5T?? Y@-1UJ:DT1EW-hTT<*  
E8      X       43750   43750           1       0        DR      0

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SIGNAL  dwb_DAT_O
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DIRECTION       output
T*
RADIX   hex
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GRID    0        1       0        1       0        16711680        0        0
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ENDGRID -1
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Clock   Unclocked
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Set     Not Used
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Clear   Not Used
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AsyncSetClear   True
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isRisingEdgeSensitive   False
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DrawAnalog      0
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NegTolerance    0
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UserSpecifiedSizeRatio  1
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VerilogCode
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11
DIRECTION       output
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GRID    0        1       0        1       0        16711680        0        0
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Clock   Unclocked
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EdgeLevel       neg
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Clear   Not Used
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ClockEnable     Not Used
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LSB     0
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E4      0        23125   23125           1       0        DR      0
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b" cU!r_\oѯg2b2/ASewqȆ2I?ͷ뵯1ٿ0Ǩ9ѱ5 47$PE8CeXeњؖ;$?P;:ɀ`@ғC#/ęFѝNA}B}qn2rb?@IϮ"
CMB7&7%DŤHj4˨а`xáe˯)%ȕ<3/st5*DTK]qqAӞ7u;?u?CϿ*
'9K]϶_?@2BC`+=OAVßB󕶇_eOVgW+o'nV\g(m WfoV/
/߯?(:T?^x? VyNsxsTFADDR[3?1:13]
E8      0        43125   43125           1       0        DR      0
BJO)DJ'$6HZl~vљg@@|=iU$EE#ZT#XP`/0њɩƀRސ)$7@p)tڜ>bR`uAЇv3x?/ /2/D/oh(}//)(`U/T`/`9~CrO=?Dq4Fs?q1y;ψ6?Ǽ?#·F5&O8OJO>nOOؿOOn       vH__/_A_S_e_w___\Y_uvd2d"W#aono=o/SeωYn!}GE OFFSET
E9      X       43625   43625           1       0        DR      0
!
s?12:0]UFU#$%U&(+-U.01235Ul4,< @%@_MD;C-_7AU2@$D7JRH<(
U2ElD7
RUlL(
SIGNAL  dwb_SEL_O
4(U1(UO"D&aU=QJf        )h"Ty+Uv'_Ʌ&aQ-
DIRECTION       output
-H*9(TYgEQ/,GuideTheDocPage-1Gesture FormatBlock NormalVisio 10Block ShadowVisio 12Block HighltVisio 11ConnectorVisio 90Dot ConnectorConnector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BoxDynamic connector.8Box.3Box.4Box.5Dynamic conn?ectorDynamic connector.10Box.2Box.24Box.33Dynamic connector.39Dynamic connector.50Dynamic connector.52Dynamic connector.9Dynamic connector.45Box.13_ 63.F
RADIX   hex
E$84C-
GRID    0        1       0        1       0        16711680        0        0
DNTG\fUtw
Uc
ENDGRID -1
u
Clock   Unclocked
UQ
EdgeLevel       neg
u
Set     Not Used
Wu
Clear   Not Used
UU4ULGv      d|,9FS`mz$<TlJcUHA[*J[*{ [ { U*,{ $[        { ?[ Ul{ ^[*t{ b*{ l[*{ p[*{ tT[ 0{ [*{ U!:{ *{ խ[*{ *W*$0[ Z:'D0I)d0)+0^'l0/00*(!        0xRf
ClockEnable     Not Used
I!:!T!!"#%%&'(*)*+!U-./0U1245UjU   
ActiveLowSetClear       True
U
UUUUl4,< @%@T_KUC-UD37AUl4,=L
AsyncSetClear   True
AJ-3G7A_*<N@KIRVgIL6uH<(
ActiveLowClockEnable    True
H<(
VhdlType        std_logic
_*<NEL
RVgq k{z
VerilogType     wire
*   g"4pFX(4
@(qb@2y
SystemCType     sc_logic
JlO:]R
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
TQU#u&T!B}U?Q
>XCO :Bm`OĭGfi$̧f'ơ#E^N,çt)\*}1Ս=|`2D:IUV
StateEquation   Hex(Inc(0,2,5))
O?LG}D5 C=d#MJ!_5,Y @Oh+'0@HhtValued Sony CustomerG(Exw
HighVoltageThreshold    5
w
LowVoltageThreshold     0
 EMF EXVISIODrawingMD ??l(@(ʦPagesMastersPage-1BoxDynamic connector8_VPID_PREVIEWS_VPID_ALTERNATENAMES_PID_LINKBASE        A
LSB     0
FMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.69qP&l    P
&" WMFC XxxjP&l EMFxl     XVISIODrawing
MSB     3
 %RL Arial%Tl!y
SignalActionType        0
@
isFallingEdgeSensitive  False
@!yLXSET 0--)%Tl!
isRisingEdgeSensitive   False
@
DrawAnalog      0
@!LXSET 1--)%RL ArialJSTFm*iWpLTSH&XOS/23VPCAG?6VDMXVp]cmapܣ1cvt ؔ88fpgmGgasp  Pglyf~(ިhdmx׏yheadfY|6hhea$hmtxRp:kernAON*PZloca%T`b       6
BooleanEquation

NegTolerance    0
@
PosTolerance    0
@b        LT...RL ArialFd$X*n2$f0FPBr,>PrRª%T`=      
S

UserSpecifiedSizeRatio  1
@
VerilogCode
@= 
LTSET--)RL ArialѰ&bҞ4dӊӰPԐ"ZՄծ4Zք֮Brע0`ؐ$لٸPڰHިAll Rights ReservedArialBoldMonotypet)%TJ
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VHDLCode
@
PROPS!
@J
LdDTLB_SETS-1TM&%%V09
:

::
%(RL Arial of the last decades of the twentieth century.  Therall treatment of curves is softer and fuller than in most industrial style sans serif faces.  Terminal strokes are cut on thdiagonal which helps to give the face a less mechanical appearti%(RL Arial in reports, presentations, magazines etc, and forplay use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
E0      V       0        0           Valid        1       0        DR      0
E1      X       3750    3750            1       0        DR      0
Thot%(RL Arialreement. You have obtained this typeface software er directly from Monotype or together with software distributed by one of Monotypes licensees.
E2      V       13125   13125       Valid       1       0        DR      0
E3      X       13625   13625           1       0        DR      0
This software is a valuablesset of Monotype. Unless you have entered into a specific licena%(RL Arialown publishing use. You may not copy or distributes software.
E4      V       23125   23125     Valid 1       0        DR      0
E5      X       23625   23625           1       0        DR      0
If you have any question concerning your rights you should review the license agreement you received with the stware or contact Monotype for a copy of the license agreement.
E6      V       33125   33125     Valid 1       0        DR      0

%(RL Arial//www.monotype.com/html/type/license.htmlNegraArial Negretatu
nArial tu
nfedArial fedFettArial FettAial Typeface  The Monotyc%(RL ArialType Solutions Inc. 1990-92. All Rights ReservedArialBoldMonotype:Arial Bold:Version 2.7 (Microsoft)Arial BoldVersion 2i%(RL Arialion plc registered in theS Pat & TM Off. and elsewhere.Monotype TypographyMonotype Type rawing Office - Robin Nicholas,s%(%RL ArialR|ҦP\׊ך&l8>޾0Z,V(R|&PV
E7      X       33625   33625           1       0        DR      0
@Bz(R%Tl[{
E8      V       43125   43125     Valid 1       0        DR      0
@
E9      X       43750   43750           1       0        DR      0
@[LXVPN 0--0%Tl{
!
@
@LXVPN 1--0%RL Arial4J5577 8`8p88:::(:8<=>@
SIGNAL  dwb_STB_O
ABCDDEFHXHhIJLLLLMNNNOOPPRRRRSU>VjWdWtWWY2Z[[^0`zceh%T`     7
DIRECTION       output

RADIX   hex
@
GRID    0        1       0        1       0        16711680        0        0
@        LT...RL Arialtttuu2u\uuuvv.vXvvww*wTw~wwwx&xPxzxxxy"yLyvzzZzz{${N{x{{{| |J|t||}}F}p}}}~~B~l~~~(\%(%T`,
Md

ENDGRID -1
@
Clock   Unclocked
@,
LTVPN!!$Tvh


EdgeLevel       neg
@
Set     Not Used
@vh
LdDTLB_SETS-1$!!!!&%%V0j        MkL L     kkL%(%RL Arial8p2bPpj8X s covered under the terms of a license agreement You have obtained this typefac %T~b
Clear   Not Used
@
ClockEnable     Not Used
@LpEFFECTIVE ADDRESSb-))-0(---000---&%%V0F6    
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%(RL Arialranting you additional rits, your use of this software is limited to your workstation fo your own publishing use. You ms%(RL Arialany question concerning yr rights you should review the license agreement you received wth the software or contact Mono        
ActiveLowSetClear       True

 !"#$%&'()*+,-./0123456789:;<=>?@ADEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijlmnopqrstuvwxyz{|}~f%(RL&" WMFC 8x Arialn be contacted at:
AsyncSetClear   True
ActiveLowClockEnable    True
USA (847) 718-0400              UK - 01144 01737 765959
VhdlType        std_logic
http://www.monotype.cmhttp://www.monotype.com/html/to%(RL ArialrdNormalNormalnyNormal1KK9NormlneNormalNormalNavadnothngArruntaNormalNormalNormalNomal. 1990-1992. All Rights Reseo%(RL Arialrosoft)ArialVersion 2.76AalMTArial TrademGSUB'JSTFm*i*\LTSH!UdOS/22kVPCLT{>C6VDMXPjZxcmapܣ.@cvt pv|0fpgmw'wgasp  Py%(RL ArialDmaxp     name6`+postƬ%E0epql
VerilogType     wire
y"yLyvzzZzz{${N{x{{{| |J|t|||}}F}p}}~~B~l~~~(\xzJ.t(%(RL Arial*<(L^p06 `.xHRdr,`B
SystemCType     sc_logic
P%(RL Arial@n(^0`>j8p2bP<pj8X rif desi, Arial contains more humanist characteristics than many of it i%(%
(%RL Arialn in most industrial style sans serif faces.  Term strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extremely versatile fily of typefaces which can be used with equal success for text, %Tl]o
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
@
StateEquation   Hex(Inc(0,2,5))
@]oLXPPN 0om--0%Tl] 
HighVoltageThreshold    5
@
LowVoltageThreshold     0
@]LXPPN 1 t--0%%T`    ,
SignalActionType        0

MSB     0
@
LSB     0
@        LT...ofRL Arialtypes licensees.
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
This software is a valuable a of Monotype. Unless you have entered into a specific license agreement granting you additional rights, your use of this softwe is limited to your workstation for your own publishing use. s %TI

DrawAnalog      0
@
BooleanEquation
@LlPPN DTLB_SETS-2 t--00)%-%--)-%TO


NegTolerance    0
@
PosTolerance    0
@O
LlPPN DTLB_SETS-1ty--00)%-%--)-%%
(&%%V0        M     LL          L%(%
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(&%%V0MLLL%(&%%W,C$L--%(&%%W,Z
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UserSpecifiedSizeRatio  1
BLB
VerilogCode
%(%%V0%%%%RL Arialontains more humanist chacteristics than many of its predecessors and as such is more intune with the mood of the last e%Txk
VHDLCode
@
PROPS!
@kL\TLB SET )%---)Tl
E0      0        3750    3750            1       0        DR      0
@
E1      1       13125   13125           1       0        DR      0
@LXINDEX00-+&%W$
E2      0        13625   13625           1       0        DR      0
a
E3      1       23125   23125           1       0        DR      0

E4      0        23625   23625           1       0        DR      0
X
E5      1       33125   33125           1       0        DR      0
%(%%V,N       =
E6      0        33625   33625           1       0        DR      0
N       
E7      1       43125   43125           1       0        DR      0
N=
E8      X       43750   43750           1       0        DR      0
N     &%%V0
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SIGNAL  dwb_ACK_I
@
DIRECTION       input
@'LTINV0-&%W$Wi@``7%(%%V,9..`9..%
(RL
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
 Arial%(%
(%%Tl8#
ENDGRID -1
@
Clock   Unclocked
@LXHIT 00)%%
(RL Arial%TX
EdgeLevel       neg
@
Set     Not Used
@LP31%%RL Arial%T`
Clear   Not Used
@
ClockEnable     Not Used
@LTlogRL Arial&" WMFC xg use. You my not copy or distribute this su%TT
ActiveLowSetClear       True
@
AsyncSetClear   True
@LP2 RL Arialt you received with the stware or contact Monotype for a copy of the license agreement.
ActiveLowClockEnable    True
Monotype can be contacted at:1%(%T 
VhdlType        std_logic
@
VerilogType     wire
@Lh(DTLB_SETS)+13$!!!!%
(RL Arial92. All Rights ReservedArialRegularMonotype:Arial lar:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArial Trademark of The Monotype Corporation plc registered in the US Pat TM Off. and elsewhere.Monotype TypographyMonotype Type Drawing S%TXI
SystemCType     sc_logic
@
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
@ILP13%%%TT
StateEquation   Hex(Inc(0,2,5))
@
HighVoltageThreshold    5
@LP0er%RL Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%Tl
LowVoltageThreshold     0
@
SignalActionType        0
@LXWAY 0:/O98.&%W${%(%%V,%RL
MSB     0
LSB     0
 Ariale distributed by one of Monotypes licensees.
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
Tsoftware is a valuable asset of Monotype. Unless you have entered into a specific license agreement granting you additional rits, your use of this software is limited to your workstation fy %Tm
DrawAnalog      0
@
BooleanEquation
@     L`DTLB MISS t0)%-7--Tl
NegTolerance    0
@
PosTolerance    0
@l     L`EXCEPTION7)-+0--)40%
(%
(RL ArialdLLLLMNNNOPPRRRRRSU>VjWdWtWWY2Z[[^0`zcehgjbl2mnn@nPn`nnnno(oRoboroooppp p0p@%TX

UserSpecifiedSizeRatio  1
@
VerilogCode
@LP12%%&%W$%(%%V,&%%W$%(&%%W$

%(&%%W$%(%%V9 
VHDLCode

PROPS!
     &%%W${%(%%V,%
(%
(%RL
E0      0        11250   11250           1       0        DR      0
E1      1       13125   13125           1       0        DR      0
 Arialre distributed by one of notypes licensees.
E2      0        21250   21250           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
This software is a valuable asset of Montype. Unless you have entered ic%Tj
E4      0        31250   31250           1       0        DR      0
@
E5      1       33125   33125           1       0        DR      0
@jLdPADDR[31:13]--000%%%%&%W(CGL>%(&%%W$53>*%(%%V,!     !!       !RL Arialent you received with theoftware or contact Monotype for a copy of the license agreement
E6      0        41250   41250           1       0        DR      0
E7      1       43125   43125           1       0        DR      0
Monotype can be contacted a %(%%T~T
E8      X       43750   43750           1       0        DR      0
@
!
@~LdPAGE OFFSETo--4-4))--)TF1
@
SIGNAL  dwb_CYC_O
@FLdPADDR[12:0]m--000%%%%
(RL ArialalNormalerty of Monotype pography and its use by you is covered under the terms of a licnse agreement. You have obtaineo%(RL Arialr together with software stributed by one of Monotypes licensees.
DIRECTION       output
RADIX   hex
This software is avaluable asset of Monotype. Unlr%(%
(RL Arialonal rights, your use of is software is limited to your workstation for your own publishng use. You may not copy or dis%T`
GRID    0        1       0        1       0        16711680        0        0
E
ENDGRID -1

Clock   Unclocked
@
EdgeLevel       neg
@
Set     Not Used
LTlogRL Arialracteristics than many of its predecessors and as  is more in tune with the mood of the last decades of the twentieth century.  The overall treatment of curves is softer and fuer than in most industrial style sans serif faces.  Terminal sch%TTF
Clear   Not Used
W
ClockEnable     Not Used

ActiveLowSetClear       True
@
AsyncSetClear   True
@F
ActiveLowClockEnable    True
LP2ilRL Arial presentations, magazines etc, and for display usenewspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/mselcome.htmlNOTIFICATION OF LICENSE AGREEMENT
VhdlType        std_logic
VerilogType     wire
This typeface ap%TX
SystemCType     sc_logic

TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
@
StateEquation   Hex(Inc(0,2,5))
@X
HighVoltageThreshold    5
Lh(DTLB_SETS)+12$!!!!&%W$      %(%&"WMFCx%V0zb
zb
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zz%RL Arial or distribute this software.
LowVoltageThreshold     0
SignalActionType        0
If you have any qion concerning your rights you should review the license agreement you received with the software or contact Monotype for a co of the license agreement.
MSB     0
LSB     0
Monotype can be contacted at:
isFallingEdgeSensitive  False

01%TY
.
isRisingEdgeSensitive   False
@
DrawAnalog      0
@LlD & A attributes0--%%%%"&%%V0`
BooleanEquation
fa
NegTolerance    0
eea
PosTolerance    0
a
UserSpecifiedSizeRatio  1
e%(%
(%RL Arialpe:Arial Regular:Version 76 (Microsoft)ArialVersion 2.76ArialMTArial Trademark of The Mnotype Corporation plc register&%T
VerilogCode
]
VHDLCode
@
PROPS!
@
E0      0        3125    3125            1       0        DR      0

E1      1       43125   43125           1       0        DR      0
L`PAGE FAULT--4-)-0%)&%W$0    B      9    9%(%%V, a
E2      0        43750   43750           1       0        DR      0
`     a
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9     `     &%%W$0  9     %(%
(%%V0mMmMMmmM%RL Arialf curves is softer and fuer than in most industrial style sans serif faces.  Terminal stokes are cut on the diagonal wh %Txv.
@
SIGNAL  dwb_ERR_I
@vL\SR[SUPV -0-0--TT4~
DIRECTION       input
@
RADIX   hex
@4LP]u&%W$               %(%%V, a
GRID    0        1       0        1       0        16711680        0        0
     a
ENDGRID -1
          &%%W$                %(%
(%
(%
(%%V0} }      }}RL ArialRRRRRSU>VjWdWtWWY2[[^0`zcehgjbl2mnn@nPn`nnnnno(oRoboroooppp p0p@pzppppqqBqlqqqrr>rhr%(%RL ArialxPxzxxxy"yLyvzzZzz{${x{{{| |J|t|||}}F}p}}}~~B~l~~~(\xzJ.t(Fn(^`%TpB 
Clock   Unclocked
@
EdgeLevel       neg
@BLXACCESS-00---Tdg        
Set     Not Used
@
Clear   Not Used
@LTTYPE)---&%W$
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%(%%V,].
.
.
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%
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H0
ClockEnable     Not Used
@
ActiveLowSetClear       True
@z
H
AsyncSetClear   True
L`PROTECTION-04)-0)40T
&2
ActiveLowClockEnable    True
@
VhdlType        std_logic
@

VerilogType     wire
L`ATTRIBUTES-))0-0)--&%W$\e%(%%V,ffRL
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 Arialecific license agreement anting you additional rights, your use of this software is limied to your workstation for yours%(%RL
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
 Arial
LowVoltageThreshold     0
If you have any questioconcerning your rights you should review the license agreement ou received with the software oe%T
2
SignalActionType        0
@
MSB     0
@     L`DMMU PAGE 0770--4-TlQL$
LSB     0
@
isFallingEdgeSensitive  False
@QLLXFAULT/)-0%)T?
isRisingEdgeSensitive   False
@
DrawAnalog      0
@     L`EXCEPTIONo-+0--)40&%W(%(%%V9
BooleanEquation



NegTolerance    0
.-C Arial???????-2
PosTolerance    0
y!SET 0--)%2
UserSpecifiedSizeRatio  1
!SET 1--)%C Arial????????????????????-2
VerilogCode
       b...C Arial?????????????????????????-2
VHDLCode
        
=SET--)* Arial?????????????????????????-2
PROPS!
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-C Arial????????????????????????-C Arial?????????????????????????-C Arial?????????????????????????-C Arial???????????5???4?????????-2 Arial????????????????????lNegr-2 ArialType Solutions Inc. 1990--2 Arialion plc registered in the--C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
E0      0        43125   43125           1       0        DR      0
[VPN 0--0%2
E1      X       43750   43750           1       0        DR      0
VPN 1--0%C Arial?????????????????????????-2
!
       ...C Arial?????????????????????????-  -2
,
VPN!!$2
SIGNAL  dwb_RTY_I
h
vDTLB_SETS-1$!!!!--$kL L     kkL--C Arial?????????????????????????-!2
DIRECTION       input
EFFECTIVE ADDRESS(-))-0(---000----
RADIX   hex
-$G
5  
5     GG
-
GRID    0        1       0        1       0        16711680        0        0
C Arialranting you additional ri-
ENDGRID -1
C Arialany question concerning y-C Arialn be contacted at:
Clock   Unclocked
EdgeLevel       neg
USA-C ArialrdNormalNormalnyNorma????-C Arialrosoft)ArialVersion 2.76A-      C Arial?????? ??????????`?- C Arial?????????????????????????-
Set     Not Used
C Arial?????????????????????????-
Clear   Not Used
       "System cpXρ/--C Arial????4???????????????????-2
ClockEnable     Not Used
o]PPN 0--0%2
ActiveLowSetClear       True
]PPN 1--0%-2
AsyncSetClear   True
       ...C Arial?????????????????????????-2
ActiveLowClockEnable    True
PPN DTLB_SETS-2--00)%-%--)-%2
VhdlType        std_logic
O
PPN DTLB_SETS-1--00)%-%--)-%---$ LL          L---        --$LLL---%L-----%Y
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---%BLB
VerilogType     wire
---$%%-C Arialontains more humanist cha-2
SystemCType     sc_logic
kTLB SET)%---)2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
INDEX00-+-%
StateEquation   Hex(Inc(0,2,5))
X
HighVoltageThreshold    5
---$N       
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!
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!
!
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Percent 100
!
!
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!
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Percent 100
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!
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Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CLOCK   CLK_RISC
CORGROUP        $$CLK_RISC_BufferRising
PERIODE 2.5
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL HIGH
CORGROUP        $$CLK_RISC_BufferFalling
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
JRISEE  0
Percent 100
JFALLE  0
!
GRID    0        1       0        2       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       internal
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
!
!
CLOCK   dwb_CLK_I
CORGROUP        $$CLK_RISC_BufferRisingFalling
PERIODE 5
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL LOW
CORGROUP        $$CLK_RISC_BufferRising
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferFalling
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRising
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferFalling
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$clk_risc_BufferRising
PROPS!
Percent 100
!
!
SIGNAL  dwb_ADR_O
CORGROUP        $$clk_risc_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$clk_risc_BufferRisingFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$clk_risc_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$clk_risc_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$clk_risc_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$clk_risc_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$clk_risc_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$clk_risc_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CLOCK   clk_risc
PROPS!
PERIODE 1
E0      V       -1      -1              1       0        DR      0
DUTY    50
E1      X       3125    3125            1       0        DR      0
OFFSETE 0
E2      V       13125   13125   Valid   1       0        DR      0
INITIAL LOW
E3      X       15625   15625           1       0        DR      0
MAXUNCERTRISE   0
!
MAXUNCERTFALL   0
MINUNCERTRISE   0
SIGNAL  dwb_DAT_I
MINUNCERTFALL   0
DIRECTION       input
JRISEE  0
RADIX   hex
JFALLE  0
GRID    0        1       0        1       0        16711680        0        0
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
ENDGRID -1
Clock
DIRECTION       input
EdgeLevel       neg
MASTERCLOCK     None
Set     Not Used
Clock   Unclocked
Clear   Not Used
EdgeLevel       neg
ClockEnable     Not Used
Set     Not Used
ActiveLowSetClear       True
Clear   Not Used
AsyncSetClear   True
ClockEnable     Not Used
ActiveLowClockEnable    True
ActiveLowSetClear       True
VhdlType        std_logic
AsyncSetClear   True
VerilogType     wire
ActiveLowClockEnable    True
SystemCType     sc_logic
VhdlType        std_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerilogType     wire
StateEquation   Hex(Inc(0,2,5))
SystemCType     sc_logic
HighVoltageThreshold    5
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LowVoltageThreshold     0
StateEquation   Hex(Inc(0,2,5))
LSB     0
HighVoltageThreshold    5
MSB     31
LowVoltageThreshold     0
SignalActionType        0
MSB     0
isFallingEdgeSensitive  False
LSB     0
isRisingEdgeSensitive   False
isFallingEdgeSensitive  False
DrawAnalog      0
isRisingEdgeSensitive   True
BooleanEquation
DrawAnalog      0
NegTolerance    0
BooleanEquation
PosTolerance    0
NegTolerance    0
UserSpecifiedSizeRatio  1
PosTolerance    0
VerilogCode
UserSpecifiedSizeRatio  1
VHDLCode
VerilogCode
VhdlMapping     DefaultVhdlMapping
VHDLCode
PROPS!
PROPS!
E0      X       13125   13125           1       0        DR      0
!
E1      V       13126   13126   Valid   1       0        DR      0
E2      X       15625   15625           1       0        DR      0
SIGNAL  dbg_wp_o[11]
!
DIRECTION       output
RADIX   hex
SIGNAL  dwb_DAT_O
GRID    0        1       0        1       0        16711680        0        0
DIRECTION       output
ENDGRID -1
RADIX   hex
Clock   Unclocked
GRID    0        1       0        1       0        16711680        0        0
EdgeLevel       neg
ENDGRID -1
Set     Not Used
Clock   Unclocked
Clear   Not Used
EdgeLevel       neg
ClockEnable     Not Used
Set     Not Used
ActiveLowSetClear       True
Clear   Not Used
AsyncSetClear   True
ClockEnable     Not Used
ActiveLowClockEnable    True
ActiveLowSetClear       True
VhdlType        std_logic
AsyncSetClear   True
VerilogType     wire
ActiveLowClockEnable    True
SystemCType     sc_logic
VhdlType        std_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerilogType     wire
StateEquation   Hex(Inc(0,2,5))
SystemCType     sc_logic
HighVoltageThreshold    5
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LowVoltageThreshold     0
StateEquation   Hex(Inc(0,2,5))
SignalActionType        0
HighVoltageThreshold    5
MSB     0
LowVoltageThreshold     0
LSB     0
LSB     0
isFallingEdgeSensitive  False
MSB     31
isRisingEdgeSensitive   False
SignalActionType        0
DrawAnalog      0
isFallingEdgeSensitive  False
BooleanEquation
isRisingEdgeSensitive   False
NegTolerance    0
DrawAnalog      0
PosTolerance    0
BooleanEquation
UserSpecifiedSizeRatio  1
NegTolerance    0
VerilogCode
PosTolerance    0
VHDLCode
UserSpecifiedSizeRatio  1
PROPS!
VerilogCode
E0      0        1750    1750            1       0        DR      0
VHDLCode
E1      1       3750    3750            1       0        DR      0
PROPS!
E2      0        4750    4750            1       0        DR      0
E0      X       3125    3125            1       0        DR      0
!
E1      V       13125   13125   Valid   1       0        DR      0
E2      X       15625   15625           1       0        DR      0
SIGNAL  dbg_bp_o
!
DIRECTION       output
RADIX   hex
SIGNAL  dwb_WE_O
GRID    0        1       0        1       0        16711680        0        0
DIRECTION       output
ENDGRID -1
RADIX   hex
Clock   Unclocked
GRID    0        1       0        1       0        16711680        0        0
EdgeLevel       neg
ENDGRID -1
Set     Not Used
Clock   Unclocked
Clear   Not Used
EdgeLevel       neg
ClockEnable     Not Used
Set     Not Used
ActiveLowSetClear       True
Clear   Not Used
AsyncSetClear   True
ClockEnable     Not Used
ActiveLowClockEnable    True
ActiveLowSetClear       True
VhdlType        std_logic
AsyncSetClear   True
VerilogType     wire
ActiveLowClockEnable    True
SystemCType     sc_logic
VhdlType        std_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerilogType     wire
StateEquation   Hex(Inc(0,2,5))
SystemCType     sc_logic
HighVoltageThreshold    5
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LowVoltageThreshold     0
StateEquation   Hex(Inc(0,2,5))
SignalActionType        0
HighVoltageThreshold    5
MSB     0
LowVoltageThreshold     0
LSB     0
SignalActionType        0
isFallingEdgeSensitive  False
MSB     0
isRisingEdgeSensitive   False
LSB     0
DrawAnalog      0
isFallingEdgeSensitive  False
BooleanEquation
isRisingEdgeSensitive   False
NegTolerance    0
DrawAnalog      0
PosTolerance    0
BooleanEquation
UserSpecifiedSizeRatio  1
NegTolerance    0
VerilogCode
PosTolerance    0
VHDLCode
UserSpecifiedSizeRatio  1
PROPS!
VerilogCode
E0      0        2750    2750            1       0        DR      0
VHDLCode
E1      1       4750    4750    If Enabled      1       0        DR      0
PROPS!
!
E0      X       3125    3125            1       0        DR      0
E1      0        3467    3467            1       0        DR      0
SIGNAL  dbg_ewt_i
E2      1       13125   13125           1       0        DR      0
DIRECTION       input
E3      0        13126   13126           1       0        DR      0
RADIX   hex
E4      X       15625   15625           1       0        DR      0
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
SIGNAL  dwb_SEL_O
EdgeLevel       neg
DIRECTION       output
Set     Not Used
RADIX   hex
Clear   Not Used
GRID    0        1       0        1       0        16711680        0        0
ClockEnable     Not Used
ENDGRID -1
ActiveLowSetClear       True
Clock   Unclocked
AsyncSetClear   True
EdgeLevel       neg
ActiveLowClockEnable    True
Set     Not Used
VhdlType        std_logic
Clear   Not Used
VerilogType     wire
ClockEnable     Not Used
SystemCType     sc_logic
ActiveLowSetClear       True
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
AsyncSetClear   True
StateEquation   Hex(Inc(0,2,5))
ActiveLowClockEnable    True
HighVoltageThreshold    5
VhdlType        std_logic
LowVoltageThreshold     0
VerilogType     wire
SignalActionType        0
SystemCType     sc_logic
MSB     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LSB     0
StateEquation   Hex(Inc(0,2,5))
isFallingEdgeSensitive  False
HighVoltageThreshold    5
isRisingEdgeSensitive   False
LowVoltageThreshold     0
DrawAnalog      0
LSB     0
BooleanEquation
MSB     3
NegTolerance    0
SignalActionType        0
PosTolerance    0
isFallingEdgeSensitive  False
UserSpecifiedSizeRatio  1
isRisingEdgeSensitive   False
VerilogCode
DrawAnalog      0
VHDLCode
BooleanEquation
PROPS!
NegTolerance    0
E0      0        1250    1250            1       0        DR      0
PosTolerance    0
E1      1       3750    3750            1       0        DR      0
UserSpecifiedSizeRatio  1
E2      0        4750    4750            1       0        DR      0
VerilogCode
!
VHDLCode
PROPS!
MARKER  MARK10
E0      X       3125    3125            1       0        DR      0
ATTACH  dbg_wp_o[11]    NULL    S1
E1      V       13125   13125   Valid   1       0        DR      0
TIME    1610.903040
E2      X       15625   15625           1       0        DR      0
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
SIGNAL  dwb_STB_O
WHILERETURN
DIRECTION       output
REPEATNUMBER
RADIX   hex
SNAPTO  0
GRID    0        1       0        1       0        16711680        0        0
COMPRESSTIME    0.000000
ENDGRID -1
COMMENT aaa
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
MARKER  MARK20
Clear   Not Used
ATTACH  dbg_bp_o        NULL    S2
ClockEnable     Not Used
TIME    2644.928640
ActiveLowSetClear       True
RELATIVETIME    0.000000
AsyncSetClear   True
DISPLAYAS       5
ActiveLowClockEnable    True
MARKERTYPE      Timebreak(Curved)
VhdlType        std_logic
WHILERETURN
VerilogType     wire
REPEATNUMBER
SystemCType     sc_logic
SNAPTO  0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
COMPRESSTIME    0.000000
StateEquation   Hex(Inc(0,2,5))
COMMENT
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
Timing Diagram Editor v7.1g - Output File
MSB     0
LSB     0
PROJECT
isFallingEdgeSensitive  False
BaseTimeUnit    1
isRisingEdgeSensitive   False
DisplayTimeUnit 2
DrawAnalog      0
TextGridX       625.000000
BooleanEquation
TextGridY       6
NegTolerance    0
EdgeGridX       625.000000
PosTolerance    0
ImportStartTime 0.000000
UserSpecifiedSizeRatio  1
ImportEndTime   281474976710656.000000
VerilogCode
TimePerPixel    17.543860
VHDLCode
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
PROPS!
ColWidths       144,216,288,423,488
E0      0        3125    3125            1       0        DR      0
ScrollPos       0.000000,0.000000,0.000000
E1      1       13125   13125           1       0        DR      0
DefDelayRule    1
E2      0        15625   15625           1       0        DR      0
NoEventOverlap  NO
!
SigLabelFontHeight      8
LabelHeight     10
SIGNAL  dwb_ACK_I
LoadLibsToMem   1
DIRECTION       input
UseFullPathNames        1
RADIX   hex
LibPath
GRID    0        1       0        1       0        16711680        0        0
EntireTime      YES
ENDGRID -1
PrintTimeSpecified      NO
Clock   Unclocked
FromTime        0
EdgeLevel       neg
ToTime  15.625
Set     Not Used
AllSignals      YES
Clear   Not Used
CurrSelSigs     NO
ClockEnable     Not Used
PrintTo 2
ActiveLowSetClear       True
PrintFileName   C:\DOCS\wb_writesingle.wmf
AsyncSetClear   True
PreviewInterchange      YES
ActiveLowClockEnable    True
PreviewTIFF5    NO
VhdlType        std_logic
UseMargins      NO
VerilogType     wire
PrintTimeLine   NO
SystemCType     sc_logic
PrintBorderBox  YES
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PrintSigNames   YES
StateEquation   Hex(Inc(0,2,5))
PrintSigNamesOnEachPage YES
HighVoltageThreshold    5
AddPreviewToEPS NO
LowVoltageThreshold     0
PreviewRes      150
SignalActionType        0
MarginLR        1
MSB     0
MifImageWidth   6.00
LSB     0
MarginTB        Auto
isFallingEdgeSensitive  False
Header  %d %t;%f;%p
isRisingEdgeSensitive   False
Footer
DrawAnalog      0
ScaleHorz       100
BooleanEquation
ScaleVert       100
NegTolerance    0
ScaleHPage      1
PosTolerance    0
PrintImage      DIAGRAM
UserSpecifiedSizeRatio  1
DefaultTimingModel      minmax
VerilogCode
DefaultClock    Unclocked
VHDLCode
DefaultEdgeLevel        neg
PROPS!
DefaultSet      Not Used
E0      0        11250   11250           1       0        DR      0
DefaultClear    Not Used
E1      1       13125   13125           1       0        DR      0
DefaultClockEnable      Not Used
E2      0        15625   15625           1       0        DR      0
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
SIGNAL  dwb_CYC_O
DefaultHold     0
DIRECTION       output
DefaultRegStartupState  unknown
RADIX   hex
DefaultPodSize  8
GRID    0        1       0        1       0        16711680        0        0
DefaultActiveLowSetClear        True
ENDGRID -1
DefaultAsyncSetClear    True
Clock   Unclocked
DefaultActiveLowClockEnable     True
EdgeLevel       neg
SigLabelFontHeight      10
Set     Not Used
PROPS!
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
STYLE
AsyncSetClear   True
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
ActiveLowClockEnable    True
DrawWndFont     DEFAULT
VhdlType        std_logic
DrawWndColor    DEFAULT
VerilogType     wire
GridWndFont     DEFAULT
SystemCType     sc_logic
GridWndColor    DEFAULT
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
StateEquation   Hex(Inc(0,2,5))
LabelWndColor   DEFAULT
HighVoltageThreshold    5
ParamDispPref   0
LowVoltageThreshold     0
ParamWndCellDisplay     0
SignalActionType        0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
MSB     0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
LSB     0
MarkerDispPref  4
isFallingEdgeSensitive  False
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
isRisingEdgeSensitive   False
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
DrawAnalog      0
SignalColor     2
BooleanEquation
LabelOffset     2
NegTolerance    0
BusDisplay      0
PosTolerance    0
WaveFormWidth   0.500000
UserSpecifiedSizeRatio  1
WaveFormColor   0
VerilogCode
InputWaveFormColor      16711680
VHDLCode
SlantedEdges    1
PROPS!
SlantAngle      75
E0      0        3125    3125            1       0        DR      0
RightJustifySigNames    1
E1      1       13125   13125           1       0        DR      0
AutosplitEnabled        1
E2      0        15625   15625           1       0        DR      0
AutosplitChar   _
!
DynamSizedSignals       1
!
SIGNAL  dwb_ERR_I
DIRECTION       input
DIAGRAMTESTBENCHSETTINGS
RADIX   hex
FilesBeforeDiagramModel
GRID    0        1       0        1       0        16711680        0        0
FilesInsideDiagramModelDeclarationSection
ENDGRID -1
AbortHdlCodeEnabled     1
Clock   Unclocked
DelayHdlCodeEnabled     1
EdgeLevel       neg
SampleHdlCodeEnabled    1
Set     Not Used
MarkerHdlCodeEnabled    1
Clear   Not Used
VerboseSamples  0
ClockEnable     Not Used
VerboseDelays   0
ActiveLowSetClear       True
VerboseFileInput        0
AsyncSetClear   True
VerboseSequenceVerification     0
ActiveLowClockEnable    True
IncludeDelayTime        1
VhdlType        std_logic
ExecuteFromTopLevel     1
VerilogType     wire
TimeOutInDiagramLengths 0
SystemCType     sc_logic
DefaultCycleClock       Unclocked
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DefaultCycleEdge        neg
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
MACROS
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        15625   15625           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  dwb_RTY_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        15625   15625           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
MARKER  MARK0
!
ATTACH  dwb_DAT_O       NULL    S4
TIME    7500.000000
CORGROUP        $$CLK_I_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_I_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
Q&l    ^&" WMFC exQ&l EMFSXVISIODrawing
 Q%RL Arial%TlWQ
CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@WQLXSET 0--)%TlW
!
@
@WLXSET 1--)%RL ArialBBdd
CORGROUP        $$CLK_I_BufferRisingFalling
uJJS%T`    
Percent 100

!
@
@        LT...RL ArialPCMK%T`s1
{

CORGROUP        $$CLK_RISC_BufferRising
@
Percent 100
@s1
LTSET--)RL Arial%T6r
2

!
@
@6r
     L`IC_SETS-1$!!!&%%V0o3
p
2
2pp
%(RL ArialFn%(RL Arial(:L^p0 `.xHRdrf,`B
CORGROUP        $$CLK_RISC_BufferFalling
PZ&L%(RL Arial0`>j8p2bP<pj8X rif design, Arial contains more humanistharacteristics than many of its predecessors and as such is most%(RL Arialr and fuller than in most industrial style sans sefaces.  Terminal strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extrely versatile family of typefaces which can be used with equal s,%(%RL Arialwww.monotype.com/html/mtname/ms_arial.htmlhttp://wonotype.com/html/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
Percent 100
!
This typeface is the property of Monotype Typograp and its use by you is covered under the terms of a license agpe%Tlo
@
CORGROUP        $$CLK_RISC_BufferRisingFalling
@oLXTAG 0pe)-4%Tl 
Percent 100
@
!
@LXTAG 1 y)-4%RL Arialishing use. You may not copy or distribute this sore.
CORGROUP        $$CLK_RISC_BufferRising
If you have any question concerning your rights you should review the license agreement you received with the software  contact Monotype for a copy of the license agreement.
Percent 100
!
Mono (%T`5       m,

CORGROUP        $$CLK_RISC_BufferFalling
@
Percent 100
@5        LT...peRL Arialypeface  The Monotype Cooration plc. Data  The Monotype Corporation plc/Type SolutionsInc. 1990-1992. All Rights Reseo%T`I

!
@
@LTTAGi)-4TO


CORGROUP        $$CLK_RISC_BufferRisingFalling
@
Percent 100
@O
     L`IC_SETS-1 0%--)-%&%%V0
!
ML
L
CORGROUP        $$CLK_I_BufferRising
L%(%
(%
(RL Arialorary sans serif design, ial contains more humanist characteristics than many of its preecessors and as such is more ino%(%
(%%Tb
Percent 100
@
!
@LpEFFECTIVE ADDRESSl-))-0(---000---&%%V0|l    
}
k 
k     }}
%(RL Arial appearance.  Arial is anxtremely versatile family of typefaces which can be used with eual success for text seBb%(RL Arial bHdB((hpvxp4>.^"RBr%(RL ArialB^,\&V4d4d* !#0%`')<)***,r-P.../133344555&%(%RL ArialEFGHIKKFK~KKL
L0MNpNNNNOPQQR*RRSSTTTWXlXY"Z@ZZZ[[[[[\]^B^_`Vaabbccde&fRf%Tpo`
CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@oLXWord 0B%%%Tp`     
!
@
@LXWord 1B%%%%T`        ,
CORGROUP        $$CLK_I_BufferRisingFalling

Percent 100
@&" WMFC E
!
@        LT...RL Arial<H*hz$bzB jt<
Hæ(ƆưǒBl˖@j͔;<%TI

CORGROUP        $$CLK_RISC_BufferRising
@
Percent 100
@LhWord IC_SETS-2B%%0%--)-%TO


!
@
@O
LhWord IC_SETS-1B%%0%--)-%%
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CORGROUP        $$CLK_RISC_BufferFalling
IM
Percent 100
LHLH
!

L%(%
(%
(&%%V0(M)L
CORGROUP        $$CLK_RISC_BufferRisingFalling
L
Percent 100
))L%(&%%W,.CZ
!
QLQ-7-7
%(&%%W,


%(&%%W$.
CORGROUP        $$CLK_I_BufferRising
@d7
Percent 100
7[%(%%V,Q^^Q7Q^Q%%V0ccc&%%666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{666666666666666666666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{666666666666666666666#6'+6/367;6?C6GK6OS6W[6_c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c6`\6XT6PL6HD6@<68460,6($6 66666666666666666666|6xt6pl6hd6`\6XT6PL6HD6@<68460,6($6 6666666666&" WMFC %6666666666|6xt6pl6hd6`\6XT6PL6HD6@<68460,6($6 666666666666        
666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}666666666666666666 
666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}666666666666666666 
666%(%RL Arial%Td
!
@
@LTDMMUHSSH&%W,C
CORGROUP        $$CLK_I_BufferFalling
L
Percent 100
%(&%%W$
!


CORGROUP        $$CLK_I_BufferRisingFalling

Percent 100
%(%%V,       =
!
       
=
CORGROUP        $$CLK_RISC_BufferRising
     &%%V0CDDD%(%RL ArialArialArialCCMSTT315b3b3a84t Arial`c
Percent 100
:yMS%Td1X
!
@
@1XLTCOMP047-&%W$qh%(%%V,o^^o^^&%%W$H
ZqQ
Qh%(%%V,*^xx^Q*^x^&%%W,Z%%c%(&%%W$%(%%V,oo%RL
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
 Arial?COMSTT315b3b3a84t#XX>C',f(QArial%TlnL
!
@
@LXHIT 00)%%
(%
(RL Arial ArialArialCCMSTT316eafa793t ArialIO?CO%TX
CORGROUP        $$CLK_RISC_BufferRisingFalling
@
Percent 100
@LP31%%%
(RL Arial#XX<KC+C(Q%(RL Ariald4d* #0%`')<)***:*,r-P.../133344555&565F66(6866707@8:8J8Z9f::;
!
;@;p;;<=R>(? %(RL ArialQR*RRSSTTTWXlXY"ZZZ[[[[[\]]^B^_`Vaabbccde&fRfgXghizjkkmooopRpbprpprrrsstpu^%T`:}
@
CORGROUP        $$CLK_I_BufferRising
@:LTlogRL Arial<`pBp2~HL4d(.f(2 <H*h%TT~
Percent 100
@
!
@~LP2RL ArialBм(R|ҦP\ך&l8>޾^0Z,V&" WMFC (R|&PPV
@%T     
CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@Ld(IC_SETS)+4$!!!%
(%TTA
!
@
@LP4%RL Arial7 8`8p88:::(:8;<=>ABCDDEFHXHhIJLLLLMNNNOOPPRRRRRSU>VjWtWWY2Z[[^0`zcehgjbl2m%TTh
CORGROUP        $$CLK_I_BufferRisingFalling
@
Percent 100
@hLP3%RL Arialu2u\uuuvv.vXvvvww*w~wwwx&xPxzxxxy"yLyvzzZzz{${N{x{{{| |J|t|||}}F}}}~~B~l~~~(\xzJ.%TT
!
@
@LP0%RL      Arial6 `.xHRdrf,`B
CORGROUP        $$CLK_RISC_BufferRising
PZ&L~f"v&N%      Tl
Percent 100
@
!
@LXWAY 0O98.&
%
CORGROUP        $$CLK_RISC_BufferFalling
%V0G*MHL)L)HHL%(
Percent 100
%
(%
(%
(%RL Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%TT"
!
@
@LP2ht%%
(%
(RL Arialype Z&L~"v&N4f@n(^0`>j8p2b%TTIm
CORGROUP        $$CLK_RISC_BufferRisingFalling
@
Percent 100
@ILP1ec%&%W,
!
CL::%(%
(%%V0
gg
g
g%RL Arial versatile family of typefaces which can be used wequal success for text setting in reports, presentations, magazines etc, and for display use in newspapers, advertising and protions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp:/el%TN

@
CORGROUP        $$CLK_I_BufferRising
@NLdWORD SELECT bB400--%-0)&%W$
Percent 100
%(%%V,:::&
!
%%V0z%(&
%%V0zz%(&%%W$ 2@))7%(%%V,.PP.).P.&%%W$
%(%%V,

&%%W$2)%(%%VA9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# &%%W$ 2))%(%%V,P)P%%V,PP)P%
(RL
CORGROUP        $$CLK_I_BufferFalling
Percent 100
 Arialesign, Arial contains morhumanist characteristics than many of its predecessors and as sch is more in tune with the mooa%(%
(  %RL     
!
 Arial is softer and fuller thain most industrial style sans se        
CORGROUP        $$CLK_I_BufferRisingFalling

 !"#%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnorstuvwxyz{|}~rif faces.  Terminal strokes ar cut on the diagonal which helpe%        Te\8
Percent 100
@
!
@e\LdTO/FROM CPUe)4)0470-0TKL
@
CORGROUP        $$CLK_RISC_BufferRising
@LpTO/FROM EXTEN I/Fr)4)047-+)-0)&%W(C^LU%(&%%W$LiU`%(%%V,W     WW       W%RL Arial#XX<K'C+C(QArialArialCC%Tdg
Percent 100
@
!
@LTBYTE--)-TxwF
@
CORGROUP        $$CLK_RISC_BufferFalling
@wFL\SELECTS--%-0)-%
(%
(RL Arial#XX<K'C+C(QArial%(RL ArialalIO?COMSTT315b3b3a84t#XX>C',f%(RL&WMFC Arial,,                  uQ42rd22dr-%T`G
Percent 100
!

@
CORGROUP        $$CLK_RISC_BufferRisingFalling
@G
Percent 100
LTlogXRL ArialXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX%TT
!

CORGROUP        $$CLK_I_BufferRising
@
Percent 100
@
!
LP2RL Arial%(      %T

CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@
!
Ld(IC_SETS)+3$!!!F.-C Arial???????-2
QWSET 0--)%2
CORGROUP        $$CLK_I_BufferRisingFalling
WSET 1--)%C Arial??-2
Percent 100
       ...C Arial???-2
!
1
sSET--)2 Arial-2
r
6    IC_SETS-1$!!!--$p
2
2pp
-C Arial-C Arial?????????????????????????-C Arial?????????????????????????-C Arial????????????4????????????--C Arial?????????????????????????-2
CORGROUP        $$CLK_RISC_BufferRising
oTAG 0)-4%2
Percent 100
TAG 1)-4%C Arial???????5???4?????????????-2
!
       5...C Arialypeface  The Monotype Co-  2
TAG)-42
CORGROUP        $$CLK_RISC_BufferFalling
O
    IC_SETS-10%--)-%-
Percent 100
-$L
!
L
L-
CORGROUP        $$CLK_RISC_BufferRisingFalling
       "System΁cčρ -
Percent 100
-
!
C Arialorary sans serif design, --
--!2
CORGROUP        $$dwb_CLK_I_BufferRising
EFFECTIVE ADDRESS-))-0(---000-----$}
k       
k     }}
-C Arial appearance.  Arial is an-C Arial?????????????-C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-        -C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
Percent 100
oWord 0B%%%2
!
Word 1B%%%-2
       ...C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
CORGROUP        $$dwb_CLK_I_BufferFalling
Word IC_SETS-2B%%0%--)-%2
Percent 100
O
Word IC_SETS-1B%%0%--)-%-
!
--$
LHLH
CORGROUP        $$dwb_CLK_I_BufferRisingFalling

Percent 100
L--
!
-
--$)L
CLOCK   CLK_RISC
L
PERIODE 2.5
))L---%QLQ-7-7
DUTY    50
---%

---%7
OFFSETE 0
7[---$^Q7Q^Q--$cc--#'+/37;?CGKOSW[_cgkosw{#'+/37;?CGKOSW[_cgkosw{#'+/37;?CGKOSW[_ccccccccccccccccccccccccccccccccccccccccc{cwcscockcgccc_c[cWcScOcKcGcCc?c;c7c3c/c+c'c#cccccccccccccccccccccccccccccccccccccccccc{cwcscockcgccc_c[cWcScOcKcGcCc?c;c7c3c/c+c'c#ccccccccccccccccccccccccc`\XTPLHD@<840,($ |xtplhd`\XTPLHD@<840,($ |xtplhd`\XTPLHD@<840,($   
!%)-159=AEIMQUY]aeimquy} 
!%)-159=AEIMQUY]aeimquy} 
--d Arial??????-
2
INITIAL HIGH
DMMUHSSH-%L
MAXUNCERTRISE   0
---%
MAXUNCERTFALL   0

MINUNCERTRISE   0
---$     
MINUNCERTFALL   0
=
JRISEE  0
     --$DDD--C Arial?????????-
2
JFALLE  0
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GRID    0        1       0        2       0        16711680        0        0
ENDGRID -1
 Arial?????u???????t-        2
DIRECTION       internal
HIT 00)%-
MASTERCLOCK     None
-
Clock   Unclocked
C Arial? ???????-
EdgeLevel       neg
2
Set     Not Used
31%%-
Clear   Not Used
! Arial-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
ClockEnable     Not Used
:log! Arial?A?A?A?A?A?A?A?A?A?A?A?A?-      2
ActiveLowSetClear       True
~22 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
AsyncSetClear   True
(IC_SETS)+4$!!!-
ActiveLowClockEnable    True
 -       2
VhdlType        std_logic
4%C Arial?????????????????????????-             2
VerilogType     wire
h3%C Arial??????????????????????w??-    2
SystemCType     sc_logic
0%S Arial?????????????????????????-
2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
WAY 0O98.--$HL)L)HHL--
StateEquation   Hex(Inc(0,2,5))
-
HighVoltageThreshold    5
-
LowVoltageThreshold     0
-C Arial????????????????????????-       2
MSB     0
2%-
LSB     0
-
isFallingEdgeSensitive  False
C Arial???????????????????????-       2
isRisingEdgeSensitive   False
I1%-%L::--
DrawAnalog      0
--$g
g
g-C Arial?????????????????????????-2
BooleanEquation
NWORD SELECTB400--%-0)-%---$::
NegTolerance    0
--$z-
PosTolerance    0
--$zz---%))7---$P.).P.--%---$
--%)---v$9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# --%))---$)P--$P)P-
UserSpecifiedSizeRatio  1
 C
VerilogCode
VHDLCode
 Arialesign, Arial contains mor--
PROPS!

-C
!
 Arial is softer and fuller tha-2
CLOCK   dwb_CLK_I
\eTO/FROM CPU)4)0470-0!2
PERIODE 5
TO/FROM EXTEN I/F)4)047-+)-0)-
DUTY    50
%LU-       - -%U`- --$WW     W-C Arial???<?K???-     
2
OFFSETE 0
BYTE--)-2
INITIAL LOW
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MAXUNCERTRISE   0
-
MAXUNCERTFALL   0
! Arial-2 Arial??-2 Arial-2
MINUNCERTRISE   0
G
MINUNCERTFALL   0
log! Arial?????????????????????????-  2
JRISEE  0
JFALLE  0
22 Arial--2
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
(IC_SETS)+3$!!!Visio (TM) Drawing
DIRECTION       input
:NTHLRl !fffMMM333$
MASTERCLOCK     None
$
Clock   Unclocked
U38@Td Arial@NWingdzs@N@tMonotype Sort+
NtSymbol5T?? Y@-1UJ:DT1EW-hTT<*  
EdgeLevel       neg

/Ub
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Set     Not Used

+$PL/^&9^$? { Ak^&,,'%/v&&       *
Clear   Not Used
1y
 )P? 2
U
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AsVsVA!gLTkY  W_W__ !`#k4lb6u`kW     *4l
ClockEnable     Not Used
4l%Y?P:?-\
#!+|QtKf2|2|2|I2wGQAUoTMeE$ttA%_8BOTOfOxOO??HO?7ܻXuW?YsU42
ActiveLowSetClear       True
T*
AsyncSetClear   True
xxx
ActiveLowClockEnable    True
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VhdlType        std_logic
<<7H1OQjPSHQywHAt///YOG$_p4b%F!8q/#P?C/N^qhE!	@d)n{r1P1	@/Oqt}Q!n=k@Ʊ셩{B'ɂXVP_0TNJg211R5P"QQ[O"P!q[rrqqӂqq¢ӁӁP¡¡Waa7$VW7P$q"$qP1q1qP>q">qPKqKqPXqXq2eqeqZ2SobZZdSTQcdPQQP1H[<k?ta}Y M/OO*Dd3qO/NkS\O9E//_      ??-??=___ѷ'sϖdI,O0R7nO&ګa̗ѫaW?O  //?*
VerilogType     wire
KϥϷϾCNa\"4FXj߲K߳BTf_/q///,ڭaRdv*<+/`bbiAnFUj?|?~/ "C??Va]?     Ia(G
SystemCType     sc_logic
rpl/YDE@a1LOpO#Q/ISGQۍBQfQaIq_Uyj(ȄBb_(_:_/^_//Q__a1_      OO-OFZOQo~MA%oCAOOMgy N_r_O7Zg@:o,Ko-XyCŮbddpddpA͟ߟ'@9K]vAB(Onl=#??6HZlƎ'᏶;M_q 2DVhzόϞϰ
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
.@Rdvߚ߬߾#}(:L^p Uɑۏ"4FXj@|X*<N`r&8J\nY////A/S/e/w///F/L//??$?6?H?Z?l?~????????O"O4OFOXOjO|OOOOOO__ 0_B_T_f________oo'o9oKo]oFxoOoooooo,>PPfx,> nBsgcEfΏ(ٴJ\nȟڟ"OeOj|@į֯(:L^pʿܿB#vXT+Sbbz@v6M_Toρ6ϱi      -?Qcuߙ߽߫ϭ,/-?eY[Ưy+=Oas1ńRZsc<Ɠ`Zl~sb6-1R##5GYk}x;6/F%/jI/[/m////)////
StateEquation   Hex(Inc(0,2,5))
??.?@?R?d?v???YTV
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HighVoltageThreshold    5
dt        '9K]oCustom ?page 0,/FBN#/#1>//?/Q/
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StateEquation   Hex(Inc(0,2,5))
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LSB     0

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SignalActionType        0
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isFallingEdgeSensitive  False
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
_y%B~FPX?Zg@bV!oYF___/_BX_`-oo'o9oBx2q|P?{_V)$\.7.3Pea$]g\
ioUk*
LowVoltageThreshold     0
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SignalActionType        0
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MSB     0
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LSB     0
__._@_R_d_v_4_______        ooњ>@@?I%qDoVohozoooooo yX`^o  nd@ܳ)+=astCH
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1ˑ|ה2qUЬ?Tf֯?\.>H$Um{{U*cՠ%2BreakpointsAJ\n!#sۚfԼ>С6Ь@׀זf;kI@@}{x?@!)Q`nĿֿ迍8η})< DC1t w9 SRuχ@ØϪ        @'EX,vo݈U2TY        )0Qd);;-|L//`-/.С7
isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
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DrawAnalog      0
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NegTolerance    0
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PosTolerance    0
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UserSpecifiedSizeRatio  1
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VerilogCode
UE,/_:-
VHDLCode
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PROPS!
L_c
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E2      1       13125   13125           1       0        DR      0
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SIGNAL  dwb_SEL_O
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DIRECTION       output
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RADIX   hex
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Clock   Unclocked
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EdgeLevel       neg
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Set     Not Used
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Clear   Not Used
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ClockEnable     Not Used
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ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True

VhdlType        std_logic

VerilogType     wire
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xx        9#(Rom%TsIaAAsI
SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X

StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
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LowVoltageThreshold     0

LSB     0
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MSB     3

SignalActionType        0
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
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NegTolerance    0

PosTolerance    0
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UserSpecifiedSizeRatio  1

VerilogCode
VHDLCode

PROPS!
 %
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RADIX   hex
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EdgeLevel       neg
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Set     Not Used
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ClockEnable     Not Used
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ActiveLowSetClear       True
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ActiveLowClockEnable    True
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VhdlType        std_logic
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VerilogType     wire

%J*!H$a'$<'<$p!'p!(t!'t!(x!'x!(|!'|!('$!'!(!'!(!G!(!     G!(!'!(!'!(!'!(!'('!('!(!'!('!(!'(!'(!'!(5!'(*!(*!(*!(#!:5ip!<|x!-mH51%H5     N@@:m@*y??/qe# v      lx!0^        RU8x!Aid/<^`$bb-t!
SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
l+    R:LOcUw*|;v!@hdv]M/W.С:Lxmu&);M_q&s%uI6?%?3i?Ӊ?u 5?U??4r?3Q!Yk}@@ b/)/;/M/_/e!mV///////??0?t&ayfb?Qo?uo?o?3OEOO(O7LO^OToONaOOOOOVT\ⱷebU@N֋   ءY$6_am6@oާK,>Pbth^._ew\LmpLDeXPja}
HighVoltageThreshold    5
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LowVoltageThreshold     0
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SignalActionType        0
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MSB     0
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LSB     0
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
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DrawAnalog      0
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NegTolerance    0
W$O!3&B0T5.F@Y&'' 2D~]t*klb7?@U;~ S    /@;v>"4F2iVr~@i6PbեF?A59V TgWRtUognVghmgo9/K/]/o//-//////?#?5??Y?t^?? 1???;SO$O6ICIP`@@'QWOiO{OOOOOOOVު@@ asDK_]_o_______I٩oף婦rdISoo~&ܿJ\nΘ8KLOWPRIO 1EXCEPT^p?ʏ9OKE,,>Pbt2Gr)WΟ(:L^pV,]Y¯cܡooYXrdYhѿ+=Oasυϩϻ@VKHIGH	ION*<@N`r߄ߖKE/AS@b;'?@.gx+4ԑ!3Ed!i
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PosTolerance    0
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UserSpecifiedSizeRatio  1
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VerilogCode
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VHDLCode
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E0      0        3125    3125            1       0        DR      0
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E1      1       13125   13125           1       0        DR      0
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SIGNAL  dwb_ACK_I
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ActiveLowSetClear       True
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AsyncSetClear   True
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VhdlType        std_logic
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
LowVoltageThreshold     0

SignalActionType        0
MSB     0
LSB     0

isFallingEdgeSensitive  False
&%W$>>%(%%V,&%%V0zGzGGz%(&%%V0)ej))jeBe)%(&%%W$VV%(&%%W,)..).%(&%%W$GG%(&%%W$e..e..%(&%%W$%(%%V,%RL Arial%TJAA
isRisingEdgeSensitive   False
L`INT [31:2] &%WX{rfYL?2'%(&%%WX{rfYL?2'%(&%%WX\~sib]\%(&%%WX\~sib^\%(&%%V0>>>>%(%RL Arial%Td&?<AA&LTICPR
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DrawAnalog      0

      
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NegTolerance    0
               
PosTolerance    0
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PROPS!
@WQLXSET 0--)%TlW
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SIGNAL  dwb_CYC_O
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DIRECTION       output
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RADIX   hex
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GRID    0        1       0        1       0        16711680        0        0
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LTSET--)RL ArialR fHH      D     n               
ENDGRID -1

Clock   Unclocked
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EdgeLevel       neg
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Set     Not Used

Clear   Not Used

ClockEnable     Not Used
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AsyncSetClear   True
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ActiveLowClockEnable    True
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VhdlType        std_logic
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VerilogType     wire
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))

HighVoltageThreshold    5
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SignalActionType        0
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MSB     0
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LSB     0
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
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DrawAnalog      0
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NegTolerance    0
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PosTolerance    0
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k     }}
%(RL Arialns, magazines etc, and for display use in newspapeadvertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/ms_welcome.htmOTIFICATION OF LICENSE AGREEMENT
VerilogCode
VHDLCode
This typeface is the prope u%(RL Arialed this typeface software either directly from Mone or together with software distributed by one of Monotypes licensees.
PROPS!
E0      0        3125    3125            1       0        DR      0
This software is a valuable asset of Monotype. Unle you have entered into a specific license agreement granting yth%(RL Arialmay not copy or distribute this software.
E1      1       13125   13125           1       0        DR      0
E2      0        15625   15625           1       0        DR      0
If yove any question concerning your rights you should review the license agreement you received with the software or contact Monote for a copy of the license agreement.
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DIRECTION       input
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RADIX   hex
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ENDGRID -1

Clock   Unclocked
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EdgeLevel       neg
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Set     Not Used
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Clear   Not Used
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ClockEnable     Not Used
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ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True
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VhdlType        std_logic

VerilogType     wire
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
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LowVoltageThreshold     0
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SignalActionType        0
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MSB     0

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666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}666666666666666666 
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LSB     0
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
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DrawAnalog      0
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NegTolerance    0

PosTolerance    0

UserSpecifiedSizeRatio  1
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E0      0        15625   15625           1       0        DR      0
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SIGNAL  dwb_RTY_I
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DIRECTION       input
@
RADIX   hex
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(RL ArialmooopRpbprpprrrssu^vvwwy zzT{{|||}}~~H:x2
GRID    0        1       0        1       0        16711680        0        0
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ENDGRID -1
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Clock   Unclocked
@LP31%%%
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EdgeLevel       neg
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Set     Not Used
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Clear   Not Used
@
ClockEnable     Not Used
@/LTlogRL Arialnnno(oRoboroooppp p@pPpzppppqqBqlqqqrr>rhrrrss:sdssstt6t`tttu2u\uuuvv.vXvvvww*wTw~%TTs
ActiveLowSetClear       True
@
AsyncSetClear   True
@sLP2RL Arialn(^`jbr**<&" WMFC (:L^p06 `.xH%T        
ActiveLowClockEnable    True
@
VhdlType        std_logic
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VerilogType     wire
@
SystemCType     sc_logic
@LP4%RL Arialore humanist characteristics than many of its predsors and as such is more in tune with the mood of the last decades of the twentieth century.  The overall treatment of curves  softer and fuller than in most industrial style sans serif fath%TTh
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
@
StateEquation   Hex(Inc(0,2,5))
@hLP3%RL Arialhumanist characteristics than many of its predeces and as such is more in tune with the mood of the last decades of the twentieth century.  The overall treatment of curves is ster and fuller than in most industrial style sans serif faces.di%TT
HighVoltageThreshold    5
@
LowVoltageThreshold     0
@LP0er%RL      Arial in reports, presentations, magazines etc, and forplay use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
SignalActionType        0
MSB     0
Thot%  Tl
LSB     0
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isFallingEdgeSensitive  False
@LXWAY 0inO98.&
isRisingEdgeSensitive   False
%
DrawAnalog      0
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BooleanEquation
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(%RL Arialour own publishing use. You may not copy or distri this software.
NegTolerance    0
PosTolerance    0
If you have any question concerning your rights you should review the license agreement you received with t software or contact Monotype for a copy of the license agreemat%TT"
UserSpecifiedSizeRatio  1
@
VerilogCode
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E0      0        15625   15625           1       0        DR      0
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RELATIVETIME    0.000000
DISPLAYAS       5
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(  %RL     
MARKERTYPE      Timebreak(Curved)
WHILERETURN
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SNAPTO  0
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COMPRESSTIME    0.000000
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DefaultClockToOutLH     0
*G#_;/UQ)8Oi5 x)hDb__ U)))DVhzF7T4FW1`DCache
DefaultClockToOutHL     0
8KB//H?6/     Q/u/=/b/y/??'?9?K?%Ǫ;O~?O5Cm[=Ўߑ>w[OF(O
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op??[[rO?KO6~SewDn h)1euPICSew?///=/a/s/////J//?'?OK?Oo95K?o\1?;gx>CO(OO!OAW_,_>_P_pb________a@{o0oBoTofoxooT@tϷo3W4kTICK TIMERo  -?QcukC);M_ˏA%bI?pWײַ{П(L*pFXGxү./ASea4ĿֿT'icfDEBUGnπϒϤ϶4"4X/|ߎߠ߲3?~/Bf?b
pEO?#?GYO}OON       j@Qr_%7I?m@?_xadf);M_qT]Uoy@QIPOWERM//(/:/L/^/p/?//T?/(/??$?6?H?l?~???_?*_?OG2Odo帟qO
DefaultSetup    0
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DefaultHold     0
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DefaultRegStartupState  unknown
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DefaultPodSize  8
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DefaultActiveLowSetClear        True
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DefaultAsyncSetClear    True
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?Qy@Qh c7tEAb~@a
DefaultActiveLowClockEnable     True
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SigLabelFontHeight      10
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PROPS!
Jpbwun`uf@"Qhh@!bbas0bbt3aQ"[QuP` 33s:vDruV0Nya8lizmzg$5{9w:vrR z_wre)Rp`U2Nw`@z3aIOaH$06iO#9VQV17U+iQ^s$aR!Weq4`6jV3oJ?UR`9*@_$DrJyD09p8T!A____       o@o-o?oQocoujooooooo %|DVqjVvA>sZsyZwC?u㷊s+5@pII}uetτݢpxƳϊ4X!.r+!3EW{՚+=Oasrmܨ̯ޯ&8J\nmᏹ-wܶul#o
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!
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STYLE

,J)System :L^p//$/6/HV/k/F/////??Y9?O]?IԘn?O?şO/^./wUFUU !"#U$'()*+Ul4,@~        6;C-3+7AU2@x 177FRH<(
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
U2Ex     77
RUlL\6@?%w7RD;U$
DrawWndFont     DEFAULT
!s["4FXj|C:\Program Files\Visio\Solution Extras\Backgrounds.vss#s[     #5GYk}C:\Program Files\Visio\Solutions\Block Dia\Basic Shapes.vss(s["4FXj|C:\Program Files\Visio\Solution Extras\Borders and Tit.vssv(B*8yC!܁+~/    ?9/U1(UO"D&aU=QJf       )h"Ty+U
DrawWndColor    DEFAULT
"_Ʌ&aQ-
GridWndFont     DEFAULT
-H*9(TYkPEQ/,GuideTheDocPage-1Gesture FormatVisio 90ConnectorVisio 00Visio 01Visio 02Visio 03Visio 10Visio 11Visio 12Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BasicBasic ShadowRectangleSchemeNameRectangle.28Rectangle.4Rectangle.5Rectangle.6Rectangle.7Rectangle.8Rectangle.9Rectangle.10Rectangle.11Dynamic conn?ectorRectangle.16Rectangle.17Rectangle.18Rectangle.24Rectangle.25_%,3:
GridWndColor    DEFAULT
E-
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
SGMU
4MULMc
LabelWndColor   DEFAULT
dMUc
ParamDispPref   0
|Mc
ParamWndCellDisplay     0
Mc
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
M     ;d      ĪM
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
M#
MarkerDispPref  4
M0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
=
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
$J
SignalColor     2
<W
LabelOffset     4
Td
BusDisplay      0
lq
WaveFormWidth   0.500000
~
WaveFormColor   0

InputWaveFormColor      16711680

SlantedEdges    1

SlantAngle      75

RightJustifySigNames    1
|Ix<\<t%*(%*8%*H%*X%*h|% y*U % A % UD *\ *t ˪* ܑ* &"U        0fx!(!*! !"#!&'()*+U^U        
AutosplitEnabled        1
U
UUUl4,@X>KC-Q5/?AUl4,v   ?
AutosplitChar   _
AJ-37A_*<N@DQ;?GRVgTRq6uH<(
DynamSizedSignals       1
H<(
!
_*<NER
@
RVg\]q &AM3'AM3(PPT)PPT1_(*'9K]o#5GYk}
//1/C/U/g/y////p@
A" }* * J"&') {z
DIAGRAMTESTBENCHSETTINGS
*   g"4pFX(S0@(xKsqR2^z     J}$Q:RT
FilesBeforeDiagramModel
Ru&O(!B  U[I>l8B>O9BNo5Ogf}$
FilesInsideDiagramModelDeclarationSection
'7SNW8)4_9J1=`2܆<kV?_, F}D$C=\g.U                            
AbortHdlCodeEnabled     1
                  
                                                            a                                !     "     #     $     %     &	'	)	*	+	,	-	.	/	0	1	2	3	4	5	6	7	8	9	:	;     <	=	>      ?     @     B C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `      c     d     e     f     g     h     i     j     k     l     n o     p     q     r     s     t     u     v     w     x     y     z     {     |     }     ~          Oh+'0@`lxValued Sony CustomerAC:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vst՜.+,D՜.+,(@LXd
PagesMastersPage-1
DelayHdlCodeEnabled     1
RectangleDynamic connector 0lx_VPID_ALTERNATENAMESB`_PID_LINKBASEA     
SampleHdlCodeEnabled    1
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
MarkerHdlCodeEnabled    1
VerboseSamples  0
PROJECT
VerboseDelays   0
BaseTimeUnit    1
VerboseFileInput        0
DisplayTimeUnit 2
VerboseSequenceVerification     0
TextGridX       250.000000
IncludeDelayTime        1
TextGridY       6
ExecuteFromTopLevel     1
EdgeGridX       250.000000
TimeOutInDiagramLengths 0
ImportStartTime 0.000000
DefaultCycleClock       Unclocked
ImportEndTime   281474976710656.000000
DefaultCycleEdge        neg
TimePerPixel    6.571429
!
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
ColWidths       144,216,288,423,488
MACROS
ScrollPos       0.000000,0.000000,0.000000
!
DefDelayRule    1
NoEventOverlap  NO
CORGROUP        $$CLK_I_BufferRising
SigLabelFontHeight      10
Percent 100
LabelHeight     12
!
LoadLibsToMem   1
UseFullPathNames        1
CORGROUP        $$CLK_I_BufferFalling
LibPath
Percent 100
EntireTime      YES
!
PrintTimeSpecified      NO
FromTime        0
CORGROUP        $$CLK_I_BufferRisingFalling
ToTime  5.75
Percent 100
AllSignals      YES
!
CurrSelSigs     NO
PrintTo 2
CORGROUP        $$CLK_I_BufferRising
PrintFileName   C:\DOCS\dbg_readwritespr.wmf
Percent 100
PreviewInterchange      YES
!
PreviewTIFF5    NO
UseMargins      NO
CORGROUP        $$CLK_I_BufferFalling
PrintTimeLine   NO
Percent 100
PrintBorderBox  YES
!
PrintSigNames   YES
PrintSigNamesOnEachPage YES
CORGROUP        $$CLK_I_BufferRisingFalling
AddPreviewToEPS NO
Percent 100
PreviewRes      150
!
MarginLR        1.25
MifImageWidth   6.00
CORGROUP        $$CLK_I_BufferRising
MarginTB        Auto
Percent 100
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
CORGROUP        $$CLK_I_BufferFalling
ScaleVert       100
Percent 100
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultClock    Unclocked
Percent 100
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
CORGROUP        $$CLK_I_BufferRising
DefaultClockEnable      Not Used
Percent 100
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
CORGROUP        $$CLK_I_BufferFalling
DefaultHold     0
Percent 100
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultAsyncSetClear    True
Percent 100
DefaultActiveLowClockEnable     True
!
SigLabelFontHeight      10
PROPS!
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
STYLE
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
CORGROUP        $$CLK_I_BufferFalling
DrawWndFont     DEFAULT
Percent 100
DrawWndColor    DEFAULT
!
GridWndFont     DEFAULT
GridWndColor    DEFAULT
CORGROUP        $$CLK_I_BufferRisingFalling
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
Percent 100
LabelWndColor   DEFAULT
!
ParamDispPref   0
ParamWndCellDisplay     0
CORGROUP        $$CLK_I_BufferRising
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Percent 100
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
MarkerDispPref  4
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
CORGROUP        $$CLK_I_BufferFalling
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
Percent 100
SignalColor     2
!
LabelOffset     4
BusDisplay      0
CORGROUP        $$CLK_I_BufferRisingFalling
WaveFormWidth   0.500000
Percent 100
WaveFormColor   0
!
InputWaveFormColor      16711680
SlantedEdges    1
CORGROUP        $$CLK_RISC_BufferRising
SlantAngle      75
Percent 100
RightJustifySigNames    1
!
AutosplitEnabled        1
AutosplitChar   _
CORGROUP        $$CLK_RISC_BufferFalling
DynamSizedSignals       1
Percent 100
!
!
DIAGRAMTESTBENCHSETTINGS
CORGROUP        $$CLK_RISC_BufferRisingFalling
FilesBeforeDiagramModel
Percent 100
FilesInsideDiagramModelDeclarationSection
!
AbortHdlCodeEnabled     1
DelayHdlCodeEnabled     1
CORGROUP        $$CLK_RISC_BufferRising
SampleHdlCodeEnabled    1
Percent 100
MarkerHdlCodeEnabled    1
!
VerboseSamples  0
VerboseDelays   0
CORGROUP        $$CLK_RISC_BufferFalling
VerboseFileInput        0
Percent 100
VerboseSequenceVerification     0
!
IncludeDelayTime        1
ExecuteFromTopLevel     1
CORGROUP        $$CLK_RISC_BufferRisingFalling
TimeOutInDiagramLengths 0
Percent 100
DefaultCycleClock       Unclocked
!
DefaultCycleEdge        neg
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
MACROS
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CLOCK   clk_risc
CORGROUP        $$CLK_RISC_BufferRisingFalling
PERIODE 1
Percent 100
DUTY    50
!
OFFSETE 4.5
INITIAL HIGH
CORGROUP        $$CLK_RISC_BufferRising
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferFalling
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       0        2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$clk_risc_BufferRising
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$clk_risc_BufferFalling
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$clk_risc_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$clk_risc_BufferRising
PROPS!
Percent 100
E5      1       7000    7000            1       0        DR      0
!
E6      0        7500    7500            1       0        DR      0
E7      1       8000    8000            1       0        DR      0
CORGROUP        $$clk_risc_BufferFalling
E9      1       9000    9000            1       0        DR      0
Percent 100
!
!
SIGNAL  rst
CORGROUP        $$clk_risc_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CLOCK   clk_risc
Clock   Unclocked
PERIODE 1
EdgeLevel       neg
DUTY    50
Set     Not Used
OFFSETE 0
Clear   Not Used
INITIAL LOW
ClockEnable     Not Used
MAXUNCERTRISE   0
ActiveLowSetClear       True
MAXUNCERTFALL   0
AsyncSetClear   True
MINUNCERTRISE   0
ActiveLowClockEnable    True
MINUNCERTFALL   0
VhdlType        std_logic
JRISEE  0
VerilogType     wire
JFALLE  0
SystemCType     sc_logic
GRID    1       1       1       2       2       16711680        0        0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ENDGRID -1
StateEquation   Hex(Inc(0,2,5))
DIRECTION       input
HighVoltageThreshold    5
MASTERCLOCK     None
LowVoltageThreshold     0
Clock   Unclocked
SignalActionType        0
EdgeLevel       neg
MSB     0
Set     Not Used
LSB     0
Clear   Not Used
isFallingEdgeSensitive  False
ClockEnable     Not Used
isRisingEdgeSensitive   False
ActiveLowSetClear       True
DrawAnalog      0
AsyncSetClear   True
BooleanEquation
ActiveLowClockEnable    True
NegTolerance    0
VhdlType        std_logic
PosTolerance    0
VerilogType     wire
UserSpecifiedSizeRatio  1
SystemCType     sc_logic
VerilogCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VHDLCode
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
E0      0        1750    1750            1       0        DR      0
LowVoltageThreshold     0
E1      1       3750    3750            1       0        DR      0
MSB     0
E2      0        5750    5750            1       0        DR      0
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
SIGNAL  dbg_dat_o
DrawAnalog      0
DIRECTION       output
BooleanEquation
RADIX   hex
NegTolerance    0
GRID    0        1       0        1       0        16711680        0        0
PosTolerance    0
ENDGRID -1
UserSpecifiedSizeRatio  1
Clock
VerilogCode
EdgeLevel       neg
VHDLCode
Set     Not Used
PROPS!
Clear   Not Used
E5      1       2500    2500            1       0        DR      0
ClockEnable     Not Used
E6      0        3000    3000            1       0        DR      0
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
SIGNAL  dbg_adr_i
VhdlType        std_logic
DIRECTION       input
VerilogType     wire
RADIX   hex
SystemCType     sc_logic
GRID    0        1       0        1       0        16711680        0        0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ENDGRID -1
StateEquation   Hex(Inc(0,2,5))
Clock   Unclocked
HighVoltageThreshold    5
EdgeLevel       neg
LowVoltageThreshold     0
Set     Not Used
LSB     0
Clear   Not Used
MSB     31
ClockEnable     Not Used
SignalActionType        0
ActiveLowSetClear       True
isFallingEdgeSensitive  False
AsyncSetClear   True
isRisingEdgeSensitive   True
ActiveLowClockEnable    True
DrawAnalog      0
VhdlType        std_logic
BooleanEquation
VerilogType     wire
NegTolerance    0
SystemCType     sc_logic
PosTolerance    0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
UserSpecifiedSizeRatio  1
StateEquation   Hex(Inc(0,2,5))
VerilogCode
HighVoltageThreshold    5
VHDLCode
LowVoltageThreshold     0
VhdlMapping     DefaultVhdlMapping
LSB     0
PROPS!
MSB     31
E0      X       1750    1750            1       0        DR      0
SignalActionType        0
E1      V       4750    4750    0x0     1       0        DR      0
isFallingEdgeSensitive  False
E2      V       5750    5750    0x4     1       0        DR      0
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
SIGNAL  dbg_op_i
NegTolerance    0
DIRECTION       input
PosTolerance    0
RADIX   hex
UserSpecifiedSizeRatio  1
GRID    0        1       0        1       0        16711680        0        0
VerilogCode
ENDGRID -1
VHDLCode
Clock   Unclocked
PROPS!
EdgeLevel       neg
E0      X       750     750             1       0        DR      0
Set     Not Used
E1      V       1750    1750    A20     1       0        DR      0
Clear   Not Used
E2      V       3750    3750    A100    1       0        DR      0
ClockEnable     Not Used
E3      X       5750    5750            1       0        DR      0
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
SIGNAL  dbg_dat_i
VhdlType        std_logic
DIRECTION       input
VerilogType     wire
RADIX   hex
SystemCType     sc_logic
GRID    0        1       0        1       0        16711680        0        0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ENDGRID -1
StateEquation   Hex(Inc(0,2,5))
Clock
HighVoltageThreshold    5
EdgeLevel       neg
LowVoltageThreshold     0
Set     Not Used
SignalActionType        0
Clear   Not Used
MSB     3
ClockEnable     Not Used
LSB     0
ActiveLowSetClear       True
isFallingEdgeSensitive  False
AsyncSetClear   True
isRisingEdgeSensitive   False
ActiveLowClockEnable    True
DrawAnalog      0
VhdlType        std_logic
BooleanEquation
VerilogType     wire
NegTolerance    0
SystemCType     sc_logic
PosTolerance    0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
UserSpecifiedSizeRatio  1
StateEquation   Hex(Inc(0,2,5))
VerilogCode
HighVoltageThreshold    5
VHDLCode
LowVoltageThreshold     0
PROPS!
LSB     0
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
MARKER  MARK0
isRisingEdgeSensitive   False
ATTACH  rst     NULL    S1
DrawAnalog      0
TIME    2750.000000
BooleanEquation
RELATIVETIME    0.000000
NegTolerance    0
DISPLAYAS       5
PosTolerance    0
MARKERTYPE      Timebreak(Curved)
UserSpecifiedSizeRatio  1
WHILERETURN
VerilogCode
REPEATNUMBER
VHDLCode
SNAPTO  0
VhdlMapping     DefaultVhdlMapping
COMPRESSTIME    0.000000
PROPS!
COMMENT
E0      X       750     750             1       0        DR      0
!
E1      V       1750    1750    D20     1       0        DR      0
E2      X       5750    5750            1       0        DR      0
1     &" WMFC S `
!
`*xKt1 EMF`*DXVISIODrawing
 \l&%'B0%V0>K=>=K=K>>=%(%(%RL Arialdx    `Exceptions
&%Tx/wI*A*A/L\CPU/DSP]&%'%V0k okoo k ko%(%RL Arial%%W$9-<<0%(&ccc,Mc,
SIGNAL  dbg_dat_o
,,H,,,,MM^,M,MM,,,,,Mr,HM(%M%T|AX*A*A|A
DIRECTION       output
L`InstuctionTdYp*A*AYLTUnit&%W$]!c``%(&%%V0kkkk%(%RL Arial
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0





%Tv*A*Av
ENDGRID -1
L`Exceptions
&%W$!%(&%%W$]!`%(&%%W$?<%(&%%W$,?2<//%(&%%W$9-?<<0%(&%%W$,"FC/%(%%V,@*V*@V@*@&%%W$QQxWTTuT%(&%%W$QT%(&%%W$
ZW%(%%V,TjTjTT&%%W$ mj#%(%%V,&&&&%RL Arial%T|Ud*A*AUL\Data MMU          Txet*A*AeL\& Cache  RL Arial                               
Clock
                  
                                                                                            !     "     #     $     %     &	'	(	)	*	+	,	-	.	/	0	1	2	3	4	5	6	8	[	:	;     <	=	>      ?     @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     \ {     ^     _     `     a     b     c     d     e     f     g     i j     k     l     m     n     o     p     q     r     s     t     u     v     w     x     y     z     | ~           %(RL Arial%T|A<P*A*AAL\Insn MMU    TxQ8`*A*AQL\& Cache,  &%W$Y[_\X\%(%%V,UQkgUQk\UgUQ&%%V0k.k..kk.%(%RL Arial
EdgeLevel       neg
     
                         
Set     Not Used
          
Clear   Not Used
ClockEnable     Not Used
                
%Tp
$*A*A
LXSystem
RL Arial


ActiveLowSetClear       True
AsyncSetClear   True
     
ActiveLowClockEnable    True

VhdlType        std_logic
                          
                               %Tp
VerilogType     wire
6*A*A
SystemCType     sc_logic
LXSystem     & %     W$[X%(     %%V,!!!%%V,Uk"UkU"U&     %     %W$AifD%( &     %     %W$AWTD%( &     %     %W$QQWTTT%( &     %     %W$ghmjjk%( &     %     %W$ghnkjk%( &     %     %W$gj%( &     %     %W$gj%( &     %     %W$QyvT%( & %     %V0uB~u~~BuBu~%(     %RL      ArialF&
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
WMFC`
StateEquation   Hex(Inc(0,2,5))
`*%      TZq*A*AZ
HighVoltageThreshold    5
L`Integer EX

T|r*A*ArL\Pipeline
&
LowVoltageThreshold     0
%
LSB     0
%V0VDDDVV%(
MSB     31
%%Td9*A*ALTGPRs
&
SignalActionType        0
%
isFallingEdgeSensitive  False
%V0uuuu%(
isRisingEdgeSensitive   True
%
(%RL Arial@?>=<;:98543210/.-,+*)('&%%T*A*A
DrawAnalog      0
L`Load/Store
Td*A*ALTUnit&
BooleanEquation
%
NegTolerance    0
%V0uuuu%(
PosTolerance    0
%
(%RL Arial%T|*A*AL\MAC Unit
&
UserSpecifiedSizeRatio  1
%
VerilogCode
W$FLII%(
VHDLCode
&
VhdlMapping     DefaultVhdlMapping
%
PROPS!
%W$F[IX%(
E0      V       -1      -1              1       0        DR      0
%%V,UkUkUUk\-B0-$>=K=K>>=--.- Ariald??????-2
E1      V       750     750     PC      1       0        DR      0
/CPU/DSP--$koo k ko-- Arial%%?W$?--2
E2      X       2750    2750            1       0        DR      0
A|
E3      V       3750    3750    D100    1       0        DR      0
Instuction
2
E4      V       4750    4750    L/S EA  1       0        DR      0
YUnit-%``---$kkk-- Arial
E5      V       5750    5750    LOAD DATA       1       0        DR      0
!
-2
v
SIGNAL  dbg_op_i
Exceptions
-%---%`---%<---%<//---%<<0---%C/---$*@V@*@--%TTuT---%T---%W---$TjTT--%j#---$&&&-
 Arial?????????????????????????-2
DIRECTION       input
UData MMU           2
RADIX   hex
e& Cache             
 Arial?????????????????????????-
 Arial????????????????-2
GRID    0        1       0        1       0        16711680        0        0
AInsn MMU  2
ENDGRID -1
Q& Cache             - %\X\- --$UQk\UgUQ- -$k..kk.-     - Arial
Clock   Unclocked
   -      2
EdgeLevel       neg

System

 Arial


Set     Not Used
Clear   Not Used
       -
ClockEnable     Not Used
2
ActiveLowSetClear       True

AsyncSetClear   True
System     -%X---$!!--$UkU"U--%fD---%TD---%TTT---%jjk---%kjk---%j---%j---%vT---$u~~BuBu~-- Arial?????????????????????????-2
ActiveLowClockEnable    True
Z
VhdlType        std_logic
Integer EX

2
VerilogType     wire
rPipeline
--$DDVV---      
2
SystemCType     sc_logic
GPRs
--$uuu-        "System΁cčρ -- Arial????????@?>=<;:98-2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X

StateEquation   Hex(Inc(0,2,5))
Load/Store

2
HighVoltageThreshold    5
Unit-
-$uuu-
-- Arial?????????????????????????-2
LowVoltageThreshold     0
MAC Unit
-
%II-
-
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SignalActionType        0
ATH2@xR| !fffMMM333?Ba$
MSB     3
$
LSB     0
U,8@Td Arial@NWingdzs@N@tMonotype Sort+
NtSymbol5T?? Y@-1TJDT1EWP-hTT<U*U       
isFallingEdgeSensitive  False
U
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isRisingEdgeSensitive   False

+PL/^&9^$? { Ak^&,",'%/v&Q&      
DrawAnalog      0
1y
 )? 2

J12?k9aUBBHEHEHEUHEHEHEH@?>?:`2BBHEHEHEHEHEHEHEH@$%O9F7AOY@;
A*sVsVAgLTkY 1 W_W__ !`#ku4lb6Pu`kW 4l
BooleanEquation
4l%Y?:?-\
*#!+|tKf*2|2|2|2wG)QUoTMeEttA%_8BOTOfOxOO??O?7   ܻuW+?sU42
NegTolerance    0
T*
PosTolerance    0
xxx
UserSpecifiedSizeRatio  1
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VerilogCode
.@Rdvk}*
VHDLCode
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P27q?߃?\.? QAqش$$$'9K]H䐾伩CjPj|xԕaIW&V03E0<kPDB!ߵ        V
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LO@{5`7Copyright 1999 Visio Corporation.  All      "s reserved.` _Sba.chm!#22430Bd9     l>0>Udd!!T
E2      V       3750    3750    READ SPR == 0x4 1       0        DR      0
<hb 
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E3      V       4750    4750    READ LSEA 0x1   1       0        DR      0
g,s724?`b?M1EY?r?91M1|;6==5P2?;zrA
E4      V       5750    5750    READ LDAT 0x2   1       0        DR      0
IB=OCq,^35/V:NAC=AK?OI="3AO<_OOKAE[6:_ L_Ij_|U|\_oo_AnHl&'n!OyaGE-szF#%JB
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SIGNAL  dbg_stall_i
-|3P7UzZ@,>R0B*
V;H<(
DIRECTION       input
H<(
RADIX   hex
UzZEt
R0B>
UFDf
h-TUU[U@@??I?`d
buoqYkQhu23u`        Connector
GRID    0        1       0        1       0        16711680        0        0
`
ENDGRID -1
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Clock   Unclocked
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EdgeLevel       neg
u
Set     Not Used
`ubA@]u
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Clear   Not Used
2rq?@I ?$%?
ClockEnable     Not Used
@"U*5L -br     ^vv"(2uI."q28v"uh9Bd&</MSz
ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True
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VhdlType        std_logic
$GGdUoB@k(bZS+B?49@0RD@.S""'/ UPxo@#?FDNTe@y
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VerilogType     wire
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SystemCType     sc_logic
?.  K]o%`
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
u2`
CJQ e"
StateEquation   Hex(Inc(0,2,5))
AAI;Aa   A
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HighVoltageThreshold    5
1f!
LowVoltageThreshold     0
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SignalActionType        0
X~Q(ei6c%A6e(;uФE)@5$+$C6CC?*3 (.bbBbwzgP@G2q?
MSB     0
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LSB     0
6&03B!2*~QŎ%e     (
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isFallingEdgeSensitive  False
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isRisingEdgeSensitive   False
UnitN
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