| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's CPU ////
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//// OR1200's CPU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
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//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
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//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
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//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
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//// ////
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//// ////
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| Line 40... |
Line 40... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_cpu.v,v $
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// $Log: or1200_cpu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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// Revision 1.16 2005/01/07 09:28:37 andreje
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// flag for l.cmov instruction added
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//
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// Revision 1.15 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.12.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.11 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.9 2002/03/29 16:29:37 lampret
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// Fixed some ports in instnatiations that were removed from the modules
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//
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// Revision 1.8 2002/03/29 15:16:54 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.7 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.6 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.19 2001/11/30 18:59:47 simons
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// *** empty log message ***
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//
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.16 2001/11/20 00:57:22 lampret
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// Fixed width of du_except.
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//
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// Revision 1.15 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.14 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.13 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.12 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.11 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.4 2001/08/17 08:01:19 lampret
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// IC enable/disable.
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//
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// Revision 1.3 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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| Line 246... |
Line 143... |
input du_write;
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input du_write;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [24:0] du_dmr1;
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input [24:0] du_dmr1;
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input du_hwbkpt;
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input du_hwbkpt;
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input du_hwbkpt_ls_r;
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input du_hwbkpt_ls_r;
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output [12:0] du_except_trig;
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output [13:0] du_except_trig;
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output [12:0] du_except_stop;
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output [13:0] du_except_stop;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] rf_dataw;
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output [dw-1:0] rf_dataw;
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output [dw-1:0] du_lsu_store_dat;
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output [dw-1:0] du_lsu_store_dat;
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output [dw-1:0] du_lsu_load_dat;
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output [dw-1:0] du_lsu_load_dat;
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|
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| Line 332... |
Line 229... |
wire ex_freeze;
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wire ex_freeze;
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wire wb_freeze;
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wire wb_freeze;
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wire [`OR1200_SEL_WIDTH-1:0] sel_a;
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wire [`OR1200_SEL_WIDTH-1:0] sel_a;
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wire [`OR1200_SEL_WIDTH-1:0] sel_b;
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wire [`OR1200_SEL_WIDTH-1:0] sel_b;
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wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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wire [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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wire [dw-1:0] rf_dataw;
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wire [dw-1:0] rf_dataw;
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wire [dw-1:0] rf_dataa;
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wire [dw-1:0] rf_dataa;
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wire [dw-1:0] rf_datab;
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wire [dw-1:0] rf_datab;
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wire [dw-1:0] muxed_a;
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wire [dw-1:0] muxed_a;
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wire [dw-1:0] muxed_b;
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wire [dw-1:0] muxed_b;
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| Line 344... |
Line 242... |
wire [dw-1:0] operand_a;
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wire [dw-1:0] operand_a;
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wire [dw-1:0] operand_b;
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wire [dw-1:0] operand_b;
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wire [dw-1:0] alu_dataout;
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wire [dw-1:0] alu_dataout;
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wire [dw-1:0] lsu_dataout;
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wire [dw-1:0] lsu_dataout;
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wire [dw-1:0] sprs_dataout;
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wire [dw-1:0] sprs_dataout;
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wire [dw-1:0] fpu_dataout;
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wire [31:0] ex_simm;
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wire [31:0] ex_simm;
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wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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wire [4:0] cust5_op;
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wire [4:0] cust5_op;
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wire [5:0] cust5_limm;
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wire [5:0] cust5_limm;
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| Line 358... |
Line 257... |
wire extend_flush;
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wire extend_flush;
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wire ex_branch_taken;
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wire ex_branch_taken;
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wire flag;
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wire flag;
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wire flagforw;
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wire flagforw;
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wire flag_we;
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wire flag_we;
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wire flagforw_alu;
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wire flag_we_alu;
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wire flag_we_alu;
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wire flagforw_fpu;
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wire flag_we_fpu;
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wire carry;
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wire carry;
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wire cyforw;
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wire cyforw;
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wire cy_we_alu;
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wire cy_we_alu;
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wire cy_we_rf;
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wire cy_we_rf;
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wire lsu_stall;
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wire lsu_stall;
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| Line 371... |
Line 273... |
wire esr_we;
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wire esr_we;
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wire pc_we;
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wire pc_we;
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wire [31:0] epcr;
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wire [31:0] epcr;
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wire [31:0] eear;
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wire [31:0] eear;
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wire [`OR1200_SR_WIDTH-1:0] esr;
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wire [`OR1200_SR_WIDTH-1:0] esr;
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wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
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wire fpcsr_we;
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wire sr_we;
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wire sr_we;
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wire [`OR1200_SR_WIDTH-1:0] to_sr;
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wire [`OR1200_SR_WIDTH-1:0] to_sr;
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wire [`OR1200_SR_WIDTH-1:0] sr;
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wire [`OR1200_SR_WIDTH-1:0] sr;
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wire except_flushpipe;
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wire except_flushpipe;
|
wire except_start;
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wire except_start;
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wire except_started;
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wire except_started;
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wire fpu_except_started;
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wire [31:0] wb_insn;
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wire [31:0] wb_insn;
|
wire sig_syscall;
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wire sig_syscall;
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wire sig_trap;
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wire sig_trap;
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wire sig_fp;
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wire [31:0] spr_dat_cfgr;
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wire [31:0] spr_dat_cfgr;
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wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_fpu;
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wire force_dslot_fetch;
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wire force_dslot_fetch;
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wire no_more_dslot;
|
wire no_more_dslot;
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wire ex_void;
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wire ex_void;
|
wire ex_spr_read;
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wire ex_spr_read;
|
wire ex_spr_write;
|
wire ex_spr_write;
|
| Line 397... |
Line 304... |
wire ex_macrc_op;
|
wire ex_macrc_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [31:0] mult_mac_result;
|
wire [31:0] mult_mac_result;
|
wire mac_stall;
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wire mac_stall;
|
wire [12:0] except_trig;
|
wire [13:0] except_trig;
|
wire [12:0] except_stop;
|
wire [13:0] except_stop;
|
wire genpc_refetch;
|
wire genpc_refetch;
|
wire rfe;
|
wire rfe;
|
wire lsu_unstall;
|
wire lsu_unstall;
|
wire except_align;
|
wire except_align;
|
wire except_dtlbmiss;
|
wire except_dtlbmiss;
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| Line 474... |
Line 381... |
assign supv = sr[`OR1200_SR_SM];
|
assign supv = sr[`OR1200_SR_SM];
|
|
|
//
|
//
|
// FLAG write enable
|
// FLAG write enable
|
//
|
//
|
assign flag_we = flag_we_alu && ~abort_mvspr;
|
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
|
|
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
|
|
|
//
|
//
|
// Instantiation of instruction fetch block
|
// Instantiation of instruction fetch block
|
//
|
//
|
or1200_genpc or1200_genpc(
|
or1200_genpc or1200_genpc(
|
| Line 567... |
Line 475... |
.mac_op(mac_op),
|
.mac_op(mac_op),
|
.shrot_op(shrot_op),
|
.shrot_op(shrot_op),
|
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.rf_addrw(rf_addrw),
|
.rf_addrw(rf_addrw),
|
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
|
.fpu_op(fpu_op),
|
.pc_we(pc_we),
|
.pc_we(pc_we),
|
.wb_insn(wb_insn),
|
.wb_insn(wb_insn),
|
.id_simm(id_simm),
|
.id_simm(id_simm),
|
.id_branch_addrtarget(id_branch_addrtarget),
|
.id_branch_addrtarget(id_branch_addrtarget),
|
.ex_branch_addrtarget(ex_branch_addrtarget),
|
.ex_branch_addrtarget(ex_branch_addrtarget),
|
| Line 661... |
Line 570... |
.shrot_op(shrot_op),
|
.shrot_op(shrot_op),
|
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.cust5_op(cust5_op),
|
.cust5_op(cust5_op),
|
.cust5_limm(cust5_limm),
|
.cust5_limm(cust5_limm),
|
.result(alu_dataout),
|
.result(alu_dataout),
|
.flagforw(flagforw),
|
.flagforw(flagforw_alu),
|
.flag_we(flag_we_alu),
|
.flag_we(flag_we_alu),
|
.cyforw(cyforw),
|
.cyforw(cyforw),
|
.cy_we(cy_we_alu),
|
.cy_we(cy_we_alu),
|
.flag(flag),
|
.flag(flag),
|
.carry(carry)
|
.carry(carry)
|
);
|
);
|
|
|
|
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
|
//
|
//
|
// Instantiation of CPU's ALU
|
// FPU's exception is being dealt with
|
|
//
|
|
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
|
|
|
|
//
|
|
// Instantiation of FPU
|
|
//
|
|
or1200_fpu or1200_fpu(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.ex_freeze(ex_freeze),
|
|
.a(operand_a),
|
|
.b(operand_b),
|
|
.fpu_op(fpu_op),
|
|
.result(fpu_dataout),
|
|
.flagforw(flagforw_fpu),
|
|
.flag_we(flag_we_fpu),
|
|
.sig_fp(sig_fp),
|
|
.except_started(fpu_except_started),
|
|
.fpcsr_we(fpcsr_we),
|
|
.fpcsr(fpcsr),
|
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
|
|
.spr_write(spr_we),
|
|
.spr_addr(spr_addr),
|
|
.spr_dat_i(spr_dat_cpu),
|
|
.spr_dat_o(spr_dat_fpu)
|
|
);
|
|
`else
|
|
assign sig_fp = 0;
|
|
assign fpcsr = 0;
|
|
`endif
|
|
|
|
|
|
//
|
|
// Instantiation of CPU's multiply unit
|
//
|
//
|
or1200_mult_mac or1200_mult_mac(
|
or1200_mult_mac or1200_mult_mac(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
| Line 741... |
Line 687... |
.epcr(epcr),
|
.epcr(epcr),
|
.eear(eear),
|
.eear(eear),
|
.esr(esr),
|
.esr(esr),
|
.except_started(except_started),
|
.except_started(except_started),
|
|
|
|
.fpcsr(fpcsr),
|
|
.fpcsr_we(fpcsr_we),
|
|
.spr_dat_fpu(spr_dat_fpu),
|
|
|
.sr_we(sr_we),
|
.sr_we(sr_we),
|
.to_sr(to_sr),
|
.to_sr(to_sr),
|
.sr(sr),
|
.sr(sr),
|
.branch_op(branch_op)
|
.branch_op(branch_op)
|
);
|
);
|
| Line 796... |
Line 746... |
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
.muxin_a(alu_dataout),
|
.muxin_a(alu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_d(ex_pc),
|
.muxin_d(ex_pc),
|
|
.muxin_e(fpu_dataout),
|
.muxout(rf_dataw),
|
.muxout(rf_dataw),
|
.muxreg(wb_forw),
|
.muxreg(wb_forw),
|
.muxreg_valid(wbforw_valid)
|
.muxreg_valid(wbforw_valid)
|
);
|
);
|
|
|
| Line 846... |
Line 797... |
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_immufault(except_immufault),
|
.sig_immufault(except_immufault),
|
.sig_tick(sig_tick),
|
.sig_tick(sig_tick),
|
|
.sig_fp(sig_fp),
|
|
.fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
|
.ex_branch_taken(ex_branch_taken),
|
.ex_branch_taken(ex_branch_taken),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_err_i(icpu_err_i),
|
.icpu_err_i(icpu_err_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_err_i(dcpu_err_i),
|
.dcpu_err_i(dcpu_err_i),
|
