URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 808 and 813

Rev 808	Rev 813
Line 88...	Line 88...
`spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done`	`spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done`
`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;	parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
	parameter boot_adr = `OR1200_BOOT_ADR;

`//`	`//`
`// I/O ports`	`// I/O ports`
`//`	`//`

Line 411...	Line 412...


`//`	`//`
`// Instantiation of instruction fetch block`	`// Instantiation of instruction fetch block`
`//`	`//`
`or1200_genpc or1200_genpc(`	`or1200_genpc #(.boot_adr(boot_adr)) or1200_genpc(`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.icpu_adr_o(icpu_adr_o),`	`.icpu_adr_o(icpu_adr_o),`
`.icpu_cycstb_o(icpu_cycstb_o),`	`.icpu_cycstb_o(icpu_cycstb_o),`
`.icpu_sel_o(icpu_sel_o),`	`.icpu_sel_o(icpu_sel_o),`