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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Instruction decode ////
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//// OR1200's Instruction decode ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Majority of instruction decoding is performed here. ////
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//// Majority of instruction decoding is performed here. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_ctrl.v,v $
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// $Log: or1200_ctrl.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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// Revision 1.13 2005/01/13 11:03:43 phoenix
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// revert to the old l.sfxxi behavior
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//
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// Revision 1.12 2005/01/07 09:31:07 andreje
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// sign/zero extension for l.sfxxi instructions corrected
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//
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// Revision 1.11 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.10 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.8.4.1 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.8 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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// Revision 1.7 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.6 2002/03/29 15:16:54 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.4 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.3 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.14 2001/11/30 18:59:17 simons
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// force_dslot_fetch does not work - allways zero.
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.12 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.11 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.10 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_ctrl(
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module or1200_ctrl
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(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe, wb_flushpipe,
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except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
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wb_flushpipe,
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id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
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id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
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id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
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id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, sel_b, id_lsu_op,
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rf_addrw, rfwb_op, fpu_op,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
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sel_b, id_lsu_op,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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multicycle, wbforw_valid, sig_syscall, sig_trap,
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multicycle, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read, ex_spr_write,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
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ex_spr_write,
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id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal
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id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal
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);
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);
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//
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//
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// I/O
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// I/O
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Line 101... |
output rf_rdb;
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output rf_rdb;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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input pc_we;
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input pc_we;
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output [31:0] wb_insn;
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output [31:0] wb_insn;
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output [31:2] id_branch_addrtarget;
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output [31:2] id_branch_addrtarget;
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output [31:2] ex_branch_addrtarget;
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output [31:2] ex_branch_addrtarget;
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output [`OR1200_SEL_WIDTH-1:0] sel_a;
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output [`OR1200_SEL_WIDTH-1:0] sel_a;
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Line 443... |
endcase
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endcase
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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multicycle = 2'h3;
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multicycle = 2'h3;
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`ifdef OR1200_FPU_IMPLEMENTED
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`OR1200_OR32_FLOAT:
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multicycle = `OR1200_FPUOP_CYCLES;
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`endif
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// Single cycle instructions
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// Single cycle instructions
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default: begin
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default: begin
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multicycle = `OR1200_ONE_CYCLE;
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multicycle = `OR1200_ONE_CYCLE;
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end
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end
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Line 598... |
`ifdef OR1200_OR32_CUST5
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`ifdef OR1200_OR32_CUST5
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// l.cust5 instructions
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// l.cust5 instructions
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`OR1200_OR32_CUST5:
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`OR1200_OR32_CUST5:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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`endif
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`endif
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`ifdef OR1200_FPU_IMPLEMENTED
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// FPU instructions
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`OR1200_OR32_FLOAT:
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sel_imm <= #1 1'b0;
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`endif
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// l.nop
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// l.nop
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`OR1200_OR32_NOP:
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`OR1200_OR32_NOP:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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// All instructions with immediates
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// All instructions with immediates
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Line 669... |
`ifdef OR1200_OR32_CUST5
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`ifdef OR1200_OR32_CUST5
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`OR1200_OR32_CUST5,
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`OR1200_OR32_CUST5,
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`endif
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`endif
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`OR1200_OR32_NOP:
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`OR1200_OR32_NOP:
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except_illegal <= #1 1'b0;
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except_illegal <= #1 1'b0;
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`ifdef OR1200_FPU_IMPLEMENTED
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`OR1200_OR32_FLOAT:
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// Check it's not a double precision instruction
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except_illegal <= #1 id_insn[`OR1200_FPUOP_DOUBLE_BIT];
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`endif
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`OR1200_OR32_ALU:
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`OR1200_OR32_ALU:
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except_illegal <= #1 1'b0
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except_illegal <= #1 1'b0
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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Line 961... |
`ifdef OR1200_OR32_CUST5
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`ifdef OR1200_OR32_CUST5
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// l.cust5 instructions
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// l.cust5 instructions
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`OR1200_OR32_CUST5:
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`OR1200_OR32_CUST5:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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`endif
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`endif
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`ifdef OR1200_FPU_IMPLEMENTED
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// FPU instructions, lf.XXX.s, except sfxx
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`OR1200_OR32_FLOAT:
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rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
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`endif
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// Instructions w/o register-file write-back
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// Instructions w/o register-file write-back
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default:
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default:
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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Line 1090... |
comp_op <= #1 4'd0;
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comp_op <= #1 4'd0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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comp_op <= #1 id_insn[24:21];
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comp_op <= #1 id_insn[24:21];
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end
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end
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`ifdef OR1200_FPU_IMPLEMENTED
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//
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// Decode of FPU ops
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//
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assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT), id_insn[`OR1200_FPUOP_WIDTH-2:0]};
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`else
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assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
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`endif
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//
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//
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// Decode of l.sys
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// Decode of l.sys
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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