URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_tag.v] - Diff between revs 258 and 481

Rev 258	Rev 481
Line 105...	Line 105...
`else	`else

`//`	`//`
`// Instantiation of TAG RAM block`	`// Instantiation of TAG RAM block`
`//`	`//`
`ifdef OR1200_DC_1W_4KB	`// Data widths are tag width plus one for valid`
`or1200_spram #`	`or1200_spram #`
`(`	`(`
`.aw(8),`	.aw(`OR1200_DCTAG),
`.dw(21 + 1)`	.dw(`OR1200_DCTAG_W + 1)
`)`	`)`
`endif
`ifdef OR1200_DC_1W_8KB
`or1200_spram #`
`(`
`.aw(9),`
`.dw(20 + 1)`
`)`
`endif
`dc_tag0`	`dc_tag0`
`(`	`(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.mbist_si_i(mbist_si_i),`	`.mbist_si_i(mbist_si_i),`