| Line 122... |
Line 122... |
//`define OR1200_ALTERA_LPM
|
//`define OR1200_ALTERA_LPM
|
//`define OR1200_XILINX_RAMB16
|
//`define OR1200_XILINX_RAMB16
|
//`define OR1200_XILINX_RAMB4
|
//`define OR1200_XILINX_RAMB4
|
//`define OR1200_XILINX_RAM32X1D
|
//`define OR1200_XILINX_RAM32X1D
|
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
|
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
|
`define OR1200_ACTEL
|
// Generic models should infer RAM blocks at synthesis time (not only effects
|
|
// single port ram.)
|
|
`define OR1200_GENERIC
|
|
|
//
|
//
|
// Do not implement Data cache
|
// Do not implement Data cache
|
//
|
//
|
`define OR1200_NO_DC
|
//`define OR1200_NO_DC
|
|
|
//
|
//
|
// Do not implement Insn cache
|
// Do not implement Insn cache
|
//
|
//
|
//`define OR1200_NO_IC
|
//`define OR1200_NO_IC
|
| Line 159... |
Line 161... |
// (consider available FPGA memory resources)
|
// (consider available FPGA memory resources)
|
//
|
//
|
//`define OR1200_IC_1W_512B
|
//`define OR1200_IC_1W_512B
|
//`define OR1200_IC_1W_4KB
|
//`define OR1200_IC_1W_4KB
|
`define OR1200_IC_1W_8KB
|
`define OR1200_IC_1W_8KB
|
`define OR1200_DC_1W_4KB
|
//`define OR1200_DC_1W_4KB
|
//`define OR1200_DC_1W_8KB
|
`define OR1200_DC_1W_8KB
|
|
|
`endif
|
`endif
|
|
|
|
|
//////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////
|
| Line 311... |
Line 313... |
// implemented there is not much point having SR[CY].
|
// implemented there is not much point having SR[CY].
|
//
|
//
|
//`define OR1200_IMPL_CY
|
//`define OR1200_IMPL_CY
|
|
|
//
|
//
|
// Implement optional l.div/l.divu instructions
|
|
//
|
|
// By default divide instructions are not implemented
|
|
// to save area and increase clock frequency. or32 C/C++
|
|
// compiler can use soft library for division.
|
|
//
|
|
// To implement divide, multiplier needs to be implemented.
|
|
//
|
|
//`define OR1200_IMPL_DIV
|
|
|
|
//
|
|
// Implement rotate in the ALU
|
// Implement rotate in the ALU
|
//
|
//
|
// At the time of writing this, or32
|
// At the time of writing this, or32
|
// C/C++ compiler doesn't generate rotate
|
// C/C++ compiler doesn't generate rotate
|
// instructions. However or32 assembler
|
// instructions. However or32 assembler
|
| Line 351... |
Line 342... |
//
|
//
|
// Implement multiplier
|
// Implement multiplier
|
//
|
//
|
// By default multiplier is implemented
|
// By default multiplier is implemented
|
//
|
//
|
//`define OR1200_MULT_IMPLEMENTED
|
`define OR1200_MULT_IMPLEMENTED
|
|
|
//
|
//
|
// Implement multiply-and-accumulate
|
// Implement multiply-and-accumulate
|
//
|
//
|
// By default MAC is implemented. To
|
// By default MAC is implemented. To
|
// implement MAC, multiplier needs to be
|
// implement MAC, multiplier needs to be
|
// implemented.
|
// implemented.
|
//
|
//
|
//`define OR1200_MAC_IMPLEMENTED
|
`define OR1200_MAC_IMPLEMENTED
|
|
|
|
//
|
|
// Implement optional l.div/l.divu instructions
|
|
//
|
|
// By default divide instructions are not implemented
|
|
// to save area and increase clock frequency. or32 C/C++
|
|
// compiler can use soft library for division.
|
|
//
|
|
// To implement divide, both multiplier and MAC needs to be implemented.
|
|
//
|
|
`define OR1200_DIV_IMPLEMENTED
|
|
|
//
|
//
|
// Low power, slower multiplier
|
// Low power, slower multiplier
|
//
|
//
|
// Select between low-power (larger) multiplier
|
// Select between low-power (larger) multiplier
|
| Line 377... |
Line 379... |
|
|
//
|
//
|
// Implement HW Single Precision FPU
|
// Implement HW Single Precision FPU
|
//
|
//
|
//`define OR1200_FPU_IMPLEMENTED
|
//`define OR1200_FPU_IMPLEMENTED
|
|
//
|
|
// Select modules for FPU
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
// FPU arithmetic module (add,sub,mul,div)
|
|
`define OR1200_FPU_ARITH_FPU100
|
|
// FPU conversion module (int-float,float-int)
|
|
`define OR1200_FPU_CONV_USSELMANN
|
|
// FPU comparison module
|
|
`define OR1200_FPU_COMP_USSELMANN
|
|
`endif
|
|
|
//
|
//
|
// Clock ratio RISC clock versus WB clock
|
// Clock ratio RISC clock versus WB clock
|
//
|
//
|
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
| Line 399... |
Line 411... |
// Type of register file RAM
|
// Type of register file RAM
|
//
|
//
|
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
|
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
|
//`define OR1200_RFRAM_TWOPORT
|
//`define OR1200_RFRAM_TWOPORT
|
//
|
//
|
// Memory macro dual port (see or1200_dpram_32x32.v)
|
// Memory macro dual port (see or1200_dpram.v)
|
`define OR1200_RFRAM_DUALPORT
|
`define OR1200_RFRAM_DUALPORT
|
|
|
//
|
//
|
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
|
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
|
//`define OR1200_RFRAM_GENERIC
|
//`define OR1200_RFRAM_GENERIC
|
| Line 469... |
Line 481... |
// Execution cycles per instruction
|
// Execution cycles per instruction
|
`define OR1200_MULTICYCLE_WIDTH 3
|
`define OR1200_MULTICYCLE_WIDTH 3
|
`define OR1200_ONE_CYCLE 3'd0
|
`define OR1200_ONE_CYCLE 3'd0
|
`define OR1200_TWO_CYCLES 3'd1
|
`define OR1200_TWO_CYCLES 3'd1
|
|
|
|
// Execution control which will "wait on" a module to finish
|
|
`define OR1200_WAIT_ON_WIDTH 2
|
|
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
|
|
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
|
|
|
// Operand MUX selects
|
// Operand MUX selects
|
`define OR1200_SEL_WIDTH 2
|
`define OR1200_SEL_WIDTH 2
|
`define OR1200_SEL_RF 2'd0
|
`define OR1200_SEL_RF 2'd0
|
`define OR1200_SEL_IMM 2'd1
|
`define OR1200_SEL_IMM 2'd1
|
`define OR1200_SEL_EX_FORW 2'd2
|
`define OR1200_SEL_EX_FORW 2'd2
|
| Line 1223... |
Line 1240... |
//
|
//
|
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
`define OR1200_DCLS 4
|
`define OR1200_DCLS 4
|
|
|
// Define to perform store refill (potential performance penalty)
|
// Define to enable default behavior of cache as write through
|
// `define OR1200_DC_STORE_REFILL
|
// Turning this off enabled write back statergy
|
|
//
|
|
`define OR1200_DC_WRITETHROUGH
|
|
|
|
// Define to enable stores from the stack not doing writethrough.
|
|
// EXPERIMENTAL
|
|
//`define OR1200_DC_NOSTACKWRITETHROUGH
|
|
|
|
// Data cache SPR definitions
|
|
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
|
|
// Data cache group SPR addresses
|
|
`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented
|
|
`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented
|
|
`define OR1200_SPRGRP_DC_DCBFR 3'd2
|
|
`define OR1200_SPRGRP_DC_DCBIR 3'd3
|
|
`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented
|
|
`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented
|
|
|
//
|
//
|
// DC configurations
|
// DC configurations
|
//
|
//
|
`ifdef OR1200_DC_1W_4KB
|
`ifdef OR1200_DC_1W_4KB
|
| Line 1246... |
Line 1279... |
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG_W 20
|
`define OR1200_DCTAG_W 20
|
`endif
|
`endif
|
|
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Store buffer (SB)
|
// Store buffer (SB)
|
//
|
//
|
|
|
| Line 1390... |
Line 1424... |
`define OR1200_VR_RES1_BITS 15:6
|
`define OR1200_VR_RES1_BITS 15:6
|
`define OR1200_VR_CFG_BITS 23:16
|
`define OR1200_VR_CFG_BITS 23:16
|
`define OR1200_VR_VER_BITS 31:24
|
`define OR1200_VR_VER_BITS 31:24
|
|
|
// VR values
|
// VR values
|
`define OR1200_VR_REV 6'h01
|
`define OR1200_VR_REV 6'h08
|
`define OR1200_VR_RES1 10'h000
|
`define OR1200_VR_RES1 10'h000
|
`define OR1200_VR_CFG 8'h00
|
`define OR1200_VR_CFG 8'h00
|
`define OR1200_VR_VER 8'h12
|
`define OR1200_VR_VER 8'h12
|
|
|
// UPR fields
|
// UPR fields
|
| Line 1407... |
Line 1441... |
`define OR1200_UPR_DUP_BITS 6
|
`define OR1200_UPR_DUP_BITS 6
|
`define OR1200_UPR_PCUP_BITS 7
|
`define OR1200_UPR_PCUP_BITS 7
|
`define OR1200_UPR_PMP_BITS 8
|
`define OR1200_UPR_PMP_BITS 8
|
`define OR1200_UPR_PICP_BITS 9
|
`define OR1200_UPR_PICP_BITS 9
|
`define OR1200_UPR_TTP_BITS 10
|
`define OR1200_UPR_TTP_BITS 10
|
`define OR1200_UPR_RES1_BITS 23:11
|
`define OR1200_UPR_FPP_BITS 11
|
|
`define OR1200_UPR_RES1_BITS 23:12
|
`define OR1200_UPR_CUP_BITS 31:24
|
`define OR1200_UPR_CUP_BITS 31:24
|
|
|
// UPR values
|
// UPR values
|
`define OR1200_UPR_UP 1'b1
|
`define OR1200_UPR_UP 1'b1
|
`ifdef OR1200_NO_DC
|
`ifdef OR1200_NO_DC
|
| Line 1432... |
Line 1467... |
`ifdef OR1200_NO_IMMU
|
`ifdef OR1200_NO_IMMU
|
`define OR1200_UPR_IMP 1'b0
|
`define OR1200_UPR_IMP 1'b0
|
`else
|
`else
|
`define OR1200_UPR_IMP 1'b1
|
`define OR1200_UPR_IMP 1'b1
|
`endif
|
`endif
|
`define OR1200_UPR_MP 1'b1 // MAC always present
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
`define OR1200_UPR_MP 1'b1
|
|
`else
|
|
`define OR1200_UPR_MP 1'b0
|
|
`endif
|
`ifdef OR1200_DU_IMPLEMENTED
|
`ifdef OR1200_DU_IMPLEMENTED
|
`define OR1200_UPR_DUP 1'b1
|
`define OR1200_UPR_DUP 1'b1
|
`else
|
`else
|
`define OR1200_UPR_DUP 1'b0
|
`define OR1200_UPR_DUP 1'b0
|
`endif
|
`endif
|
| Line 1454... |
Line 1493... |
`ifdef OR1200_TT_IMPLEMENTED
|
`ifdef OR1200_TT_IMPLEMENTED
|
`define OR1200_UPR_TTP 1'b1
|
`define OR1200_UPR_TTP 1'b1
|
`else
|
`else
|
`define OR1200_UPR_TTP 1'b0
|
`define OR1200_UPR_TTP 1'b0
|
`endif
|
`endif
|
`define OR1200_UPR_RES1 13'h0000
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
`define OR1200_UPR_FPP 1'b1
|
|
`else
|
|
`define OR1200_UPR_FPP 1'b0
|
|
`endif
|
|
`define OR1200_UPR_RES1 12'h000
|
`define OR1200_UPR_CUP 8'h00
|
`define OR1200_UPR_CUP 8'h00
|
|
|
// CPUCFGR fields
|
// CPUCFGR fields
|
`define OR1200_CPUCFGR_NSGF_BITS 3:0
|
`define OR1200_CPUCFGR_NSGF_BITS 3:0
|
`define OR1200_CPUCFGR_HGF_BITS 4
|
`define OR1200_CPUCFGR_HGF_BITS 4
|
| Line 1476... |
Line 1520... |
`else
|
`else
|
`define OR1200_CPUCFGR_HGF 1'b0
|
`define OR1200_CPUCFGR_HGF 1'b0
|
`endif
|
`endif
|
`define OR1200_CPUCFGR_OB32S 1'b1
|
`define OR1200_CPUCFGR_OB32S 1'b1
|
`define OR1200_CPUCFGR_OB64S 1'b0
|
`define OR1200_CPUCFGR_OB64S 1'b0
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
`define OR1200_CPUCFGR_OF32S 1'b1
|
|
`else
|
`define OR1200_CPUCFGR_OF32S 1'b0
|
`define OR1200_CPUCFGR_OF32S 1'b0
|
|
`endif
|
|
|
`define OR1200_CPUCFGR_OF64S 1'b0
|
`define OR1200_CPUCFGR_OF64S 1'b0
|
`define OR1200_CPUCFGR_OV64S 1'b0
|
`define OR1200_CPUCFGR_OV64S 1'b0
|
`define OR1200_CPUCFGR_RES1 22'h000000
|
`define OR1200_CPUCFGR_RES1 22'h000000
|
|
|
// DMMUCFGR fields
|
// DMMUCFGR fields
|
| Line 1573... |
Line 1622... |
`define OR1200_DCCFGR_RES1 17'h00000
|
`define OR1200_DCCFGR_RES1 17'h00000
|
`else
|
`else
|
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
|
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
|
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
|
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
|
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
|
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
|
|
`ifdef OR1200_DC_WRITETHROUGH
|
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
|
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
|
|
`else
|
|
`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
|
|
`endif
|
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
|
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
|
`ifdef OR1200_DC_WRITETHROUGH
|
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
|
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
|
|
`else
|
|
`define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl.
|
|
`endif
|
`define OR1200_DCCFGR_RES1 17'h00000
|
`define OR1200_DCCFGR_RES1 17'h00000
|
`endif
|
`endif
|
|
|
// ICCFGR fields
|
// ICCFGR fields
|
`define OR1200_ICCFGR_NCW_BITS 2:0
|
`define OR1200_ICCFGR_NCW_BITS 2:0
|
| Line 1648... |
Line 1705... |
// Boot Address Selection //
|
// Boot Address Selection //
|
// This only changes where the initial reset occurs. EPH setting is still //
|
// This only changes where the initial reset occurs. EPH setting is still //
|
// used to determine where vectors are located. //
|
// used to determine where vectors are located. //
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Boot from 0xf0000100
|
// Boot from 0xf0000100
|
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
|
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
|
`define OR1200_BOOT_ADR 32'hf0000100
|
//`define OR1200_BOOT_ADR 32'hf0000100
|
// Boot from 0x100
|
// Boot from 0x100
|
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
|
`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
|
// `define OR1200_BOOT_ADR 32'h00000100
|
`define OR1200_BOOT_ADR 32'h00000100
|
|
|
No newline at end of file
|
No newline at end of file
|
