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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 808 and 813

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Rev 808 Rev 813
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//                                                                           //
//                                                                           //
// Allows a definable boot address, potentially different to the usual reset //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired.                  //
// vector to allow for power-on code to be run, if desired.                  //
//                                                                           //
//                                                                           //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
 
//                                                                           //
//                                                                           //
// For default reset behavior uncomment the settings under the "Boot 0x100"  //
// For default reset behavior uncomment the settings under the "Boot 0x100"  //
// comment below.                                                            //
// comment below.                                                            //
//                                                                           //
//                                                                           //
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
// Boot from 0xf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
 
//`define OR1200_BOOT_ADR 32'hf0000100
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
// Boot from 0x100
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
 
 `define OR1200_BOOT_ADR 32'h00000100
 `define OR1200_BOOT_ADR 32'h00000100
 
 
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