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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu.v] - Diff between revs 260 and 358

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Rev 260	Rev 358
Line 191...	Line 191...
`always @(posedge clk)`	`always @(posedge clk)`
`if (fpu_check_op)`	`if (fpu_check_op)`
fpu_op_r <= {1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]};	fpu_op_r <= {1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]};

`// Indicate new FPU op`	`// Indicate new FPU op`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`fpu_op_valid_re <= 0;`	`fpu_op_valid_re <= 0;`
`else if (fpu_op_valid_re)`	`else if (fpu_op_valid_re)`
`fpu_op_valid_re <= 0;`	`fpu_op_valid_re <= 0;`
`else if (fpu_check_op)`	`else if (fpu_check_op)`
`fpu_op_valid_re <= 1;`	`fpu_op_valid_re <= 1;`

`//`	`//`
`// FPCSR system group register implementation`	`// FPCSR system group register implementation`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`fpcsr_r <= 0;`	`fpcsr_r <= 0;`
`else`	`else`
`begin`	`begin`
`if (fpcsr_we)`	`if (fpcsr_we)`
fpcsr_r <= b[`OR1200_FPCSR_WIDTH-1:0];	fpcsr_r <= b[`OR1200_FPCSR_WIDTH-1:0];
Line 234...	Line 234...
fpcsr_r[`OR1200_FPCSR_DZF] <= (dbz & fpu_op_r_is_arith);	fpcsr_r[`OR1200_FPCSR_DZF] <= (dbz & fpu_op_r_is_arith);
`end // if (fpu_arith_done \| fpu_conv_done)`	`end // if (fpu_arith_done \| fpu_conv_done)`
`if (except_started)`	`if (except_started)`
fpcsr_r[`OR1200_FPCSR_FPEE] <= 0;	fpcsr_r[`OR1200_FPCSR_FPEE] <= 0;
`end // else: !if(rst)`	`end // else: !if(rst)`
`end // always @ (posedge clk or posedge rst)`	end // always @ (posedge clk or `OR1200_RST_EVENT rst)

`//`	`//`
`// Comparison flag generation`	`// Comparison flag generation`
`//`	`//`
`always @*`	`always @*`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu.v] - Diff between revs 260 and 358