//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200 FPU arith ////
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//// OR1200 FPU arith ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Wrapper for floating point arithmetic units. ////
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//// Wrapper for floating point arithmetic units. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - lf.rem.s and lf.madd.s instruction support ////
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//// - lf.rem.s and lf.madd.s instruction support ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Original design (FPU100) - ////
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//// - Original design (FPU100) - ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// Julius Baxter, julius@opencores.org ////
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//// Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2006, 2010
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// Copyright (C) 2006, 2010
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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module or1200_fpu_arith
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module or1200_fpu_arith
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(
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(
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clk_i,
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clk_i,
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opa_i,
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opa_i,
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opb_i,
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opb_i,
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fpu_op_i,
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fpu_op_i,
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rmode_i,
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rmode_i,
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output_o,
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output_o,
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start_i,
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start_i,
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ready_o,
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ready_o,
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ine_o,
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ine_o,
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overflow_o,
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overflow_o,
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underflow_o,
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underflow_o,
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div_zero_o,
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div_zero_o,
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inf_o,
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inf_o,
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zero_o,
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zero_o,
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qnan_o,
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qnan_o,
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snan_o
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snan_o
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);
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);
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parameter FP_WIDTH = 32;
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parameter FP_WIDTH = 32;
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parameter MUL_SERIAL = 1; // 0 for parallel multiplier, 1 for serial
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parameter MUL_SERIAL = 1; // 0 for parallel multiplier, 1 for serial
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parameter MUL_COUNT = 34; //11 for parallel multiplier, 34 for serial
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parameter MUL_COUNT = 34; //11 for parallel multiplier, 34 for serial
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parameter FRAC_WIDTH = 23;
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parameter FRAC_WIDTH = 23;
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parameter EXP_WIDTH = 8;
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parameter EXP_WIDTH = 8;
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parameter ZERO_VECTOR = 31'd0;
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parameter ZERO_VECTOR = 31'd0;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter QNAN = 31'b11111111_10000000000000000000000;
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parameter QNAN = 31'b11111111_10000000000000000000000;
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parameter SNAN = 31'b11111111_00000000000000000000001;
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parameter SNAN = 31'b11111111_00000000000000000000001;
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// fpu operations (fpu_op_i):
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// fpu operations (fpu_op_i):
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// ========================
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// ========================
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// 000 = add,
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// 000 = add,
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// 001 = substract,
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// 001 = substract,
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// 010 = multiply,
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// 010 = multiply,
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// 011 = divide,
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// 011 = divide,
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// 100 = square root - DISABLED - JPB
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// 100 = square root - DISABLED - JPB
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// 101 = unused
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// 101 = unused
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// 110 = unused
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// 110 = unused
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// 111 = unused
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// 111 = unused
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// Rounding Mode:
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// Rounding Mode:
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// ==============
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// ==============
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// 00 = round to nearest even (default),
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// 00 = round to nearest even (default),
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// 01 = round to zero,
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// 01 = round to zero,
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// 10 = round up,
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// 10 = round up,
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// 11 = round down
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// 11 = round down
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input clk_i;
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input clk_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opb_i;
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input [FP_WIDTH-1:0] opb_i;
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input [2:0] fpu_op_i;
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input [2:0] fpu_op_i;
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input [1:0] rmode_i;
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input [1:0] rmode_i;
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input start_i;
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input start_i;
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output reg ready_o;
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output reg ready_o;
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output reg [FP_WIDTH-1:0] output_o;
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output reg [FP_WIDTH-1:0] output_o;
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output reg ine_o;
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output reg ine_o;
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output reg overflow_o;
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output reg overflow_o;
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output reg underflow_o;
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output reg underflow_o;
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output reg div_zero_o;
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output reg div_zero_o;
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output reg inf_o;
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output reg inf_o;
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output reg zero_o;
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output reg zero_o;
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output reg qnan_o;
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output reg qnan_o;
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output reg snan_o;
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output reg snan_o;
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reg [FP_WIDTH-1:0] s_opa_i;
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reg [FP_WIDTH-1:0] s_opa_i;
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reg [FP_WIDTH-1:0] s_opb_i;
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reg [FP_WIDTH-1:0] s_opb_i;
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reg [2:0] s_fpu_op_i;
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reg [2:0] s_fpu_op_i;
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reg [1:0] s_rmode_i;
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reg [1:0] s_rmode_i;
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reg s_start_i;
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reg s_start_i;
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reg [5:0] s_count; // Max value of 64
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reg [5:0] s_count; // Max value of 64
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reg [FP_WIDTH-1:0] s_output1;
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reg [FP_WIDTH-1:0] s_output1;
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reg [FP_WIDTH-1:0] s_output_o; // Comb
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reg [FP_WIDTH-1:0] s_output_o; // Comb
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reg s_ine_o;
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reg s_ine_o;
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wire s_overflow_o,
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wire s_overflow_o,
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s_underflow_o,
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s_underflow_o,
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s_div_zero_o,
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s_div_zero_o,
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s_inf_o, s_zero_o, s_qnan_o, s_snan_o;
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s_inf_o, s_zero_o, s_qnan_o, s_snan_o;
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wire s_infa, s_infb;
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wire s_infa, s_infb;
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parameter t_state_waiting = 0,
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parameter t_state_waiting = 0,
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t_state_busy = 1;
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t_state_busy = 1;
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reg s_state;
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reg s_state;
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//// ***Add/Substract units signals***
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//// ***Add/Substract units signals***
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wire [27:0] prenorm_addsub_fracta_28_o;
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wire [27:0] prenorm_addsub_fracta_28_o;
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wire [27:0] prenorm_addsub_fractb_28_o;
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wire [27:0] prenorm_addsub_fractb_28_o;
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wire [7:0] prenorm_addsub_exp_o;
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wire [7:0] prenorm_addsub_exp_o;
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wire [27:0] addsub_fract_o;
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wire [27:0] addsub_fract_o;
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wire addsub_sign_o;
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wire addsub_sign_o;
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wire [31:0] postnorm_addsub_output_o;
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wire [31:0] postnorm_addsub_output_o;
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wire postnorm_addsub_ine_o;
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wire postnorm_addsub_ine_o;
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//// ***Multiply units signals***
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//// ***Multiply units signals***
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wire [9:0] pre_norm_mul_exp_10;
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wire [9:0] pre_norm_mul_exp_10;
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wire [23:0] pre_norm_mul_fracta_24 ;
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wire [23:0] pre_norm_mul_fracta_24 ;
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wire [23:0] pre_norm_mul_fractb_24 ;
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wire [23:0] pre_norm_mul_fractb_24 ;
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wire [47:0] mul_fract_48;
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wire [47:0] mul_fract_48;
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wire [47:0] mul_24_fract_48;
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wire [47:0] mul_24_fract_48;
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wire mul_24_sign;
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wire mul_24_sign;
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wire [47:0] serial_mul_fract_48;
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wire [47:0] serial_mul_fract_48;
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wire serial_mul_sign;
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wire serial_mul_sign;
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wire mul_sign;
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wire mul_sign;
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wire [31:0] post_norm_mul_output ;
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wire [31:0] post_norm_mul_output ;
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wire post_norm_mul_ine;
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wire post_norm_mul_ine;
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//// ***Division units signals***
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//// ***Division units signals***
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wire [49:0] pre_norm_div_dvdnd;
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wire [49:0] pre_norm_div_dvdnd;
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wire [26:0] pre_norm_div_dvsor;
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wire [26:0] pre_norm_div_dvsor;
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wire [EXP_WIDTH+1:0] pre_norm_div_exp;
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wire [EXP_WIDTH+1:0] pre_norm_div_exp;
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wire [26:0] serial_div_qutnt;
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wire [26:0] serial_div_qutnt;
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wire [26:0] serial_div_rmndr;
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wire [26:0] serial_div_rmndr;
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wire serial_div_sign;
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wire serial_div_sign;
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wire serial_div_div_zero;
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wire serial_div_div_zero;
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wire [31:0] post_norm_div_output;
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wire [31:0] post_norm_div_output;
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wire post_norm_div_ine;
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wire post_norm_div_ine;
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//// ***Square units***
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//// ***Square units***
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wire [51:0] pre_norm_sqrt_fracta_o;
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wire [51:0] pre_norm_sqrt_fracta_o;
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wire [7:0] pre_norm_sqrt_exp_o;
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wire [7:0] pre_norm_sqrt_exp_o;
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wire [25:0] sqrt_sqr_o;
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wire [25:0] sqrt_sqr_o;
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wire sqrt_ine_o;
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wire sqrt_ine_o;
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wire [31:0] post_norm_sqrt_output ;
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wire [31:0] post_norm_sqrt_output ;
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wire post_norm_sqrt_ine_o;
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wire post_norm_sqrt_ine_o;
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//***Add/Substract units***
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//***Add/Substract units***
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or1200_fpu_pre_norm_addsub fpu_prenorm_addsub
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or1200_fpu_pre_norm_addsub fpu_prenorm_addsub
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.opa_i(s_opa_i) ,
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.opa_i(s_opa_i) ,
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.opb_i(s_opb_i) ,
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.opb_i(s_opb_i) ,
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.fracta_28_o(prenorm_addsub_fracta_28_o) ,
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.fracta_28_o(prenorm_addsub_fracta_28_o) ,
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.fractb_28_o(prenorm_addsub_fractb_28_o) ,
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.fractb_28_o(prenorm_addsub_fractb_28_o) ,
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.exp_o(prenorm_addsub_exp_o) );
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.exp_o(prenorm_addsub_exp_o) );
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or1200_fpu_addsub fpu_addsub
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or1200_fpu_addsub fpu_addsub
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.fpu_op_i(s_fpu_op_i[0]),
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.fpu_op_i(s_fpu_op_i[0]),
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.fracta_i(prenorm_addsub_fracta_28_o) ,
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.fracta_i(prenorm_addsub_fracta_28_o) ,
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.fractb_i(prenorm_addsub_fractb_28_o) ,
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.fractb_i(prenorm_addsub_fractb_28_o) ,
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.signa_i( s_opa_i[31]),
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.signa_i( s_opa_i[31]),
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.signb_i( s_opb_i[31]),
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.signb_i( s_opb_i[31]),
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.fract_o(addsub_fract_o) ,
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.fract_o(addsub_fract_o) ,
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.sign_o(addsub_sign_o) );
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.sign_o(addsub_sign_o) );
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or1200_fpu_post_norm_addsub fpu_postnorm_addsub
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or1200_fpu_post_norm_addsub fpu_postnorm_addsub
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.opa_i(s_opa_i) ,
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.opa_i(s_opa_i) ,
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.opb_i(s_opb_i) ,
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.opb_i(s_opb_i) ,
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.fract_28_i(addsub_fract_o) ,
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.fract_28_i(addsub_fract_o) ,
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.exp_i(prenorm_addsub_exp_o) ,
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.exp_i(prenorm_addsub_exp_o) ,
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.sign_i(addsub_sign_o) ,
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.sign_i(addsub_sign_o) ,
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.fpu_op_i(s_fpu_op_i[0]),
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.fpu_op_i(s_fpu_op_i[0]),
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.rmode_i(s_rmode_i) ,
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.rmode_i(s_rmode_i) ,
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.output_o(postnorm_addsub_output_o) ,
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.output_o(postnorm_addsub_output_o) ,
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.ine_o(postnorm_addsub_ine_o)
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.ine_o(postnorm_addsub_ine_o)
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);
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);
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//***Multiply units***
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//***Multiply units***
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or1200_fpu_pre_norm_mul fpu_pre_norm_mul
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or1200_fpu_pre_norm_mul fpu_pre_norm_mul
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.opa_i(s_opa_i),
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.opa_i(s_opa_i),
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.opb_i(s_opb_i),
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.opb_i(s_opb_i),
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.exp_10_o(pre_norm_mul_exp_10),
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.exp_10_o(pre_norm_mul_exp_10),
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.fracta_24_o(pre_norm_mul_fracta_24),
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.fracta_24_o(pre_norm_mul_fracta_24),
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.fractb_24_o(pre_norm_mul_fractb_24));
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.fractb_24_o(pre_norm_mul_fractb_24));
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/*
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/*
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mul_24 i_mul_24
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mul_24 i_mul_24
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.fracta_i(pre_norm_mul_fracta_24) ,
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.fracta_i(pre_norm_mul_fracta_24) ,
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.fractb_i(pre_norm_mul_fractb_24) ,
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.fractb_i(pre_norm_mul_fractb_24) ,
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.signa_i(s_opa_i[31]),
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.signa_i(s_opa_i[31]),
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.signb_i(s_opb_i[31]),
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.signb_i(s_opb_i[31]),
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.start_i(start_i) ,
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.start_i(start_i) ,
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.fract_o(mul_24_fract_48) ,
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.fract_o(mul_24_fract_48) ,
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.sign_o(mul_24_sign) ,
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.sign_o(mul_24_sign) ,
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.ready_o() );
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.ready_o() );
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*/
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*/
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// Serial multiply is default and only one included here
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// Serial multiply is default and only one included here
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or1200_fpu_mul fpu_mul
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or1200_fpu_mul fpu_mul
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.fracta_i(pre_norm_mul_fracta_24) ,
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.fracta_i(pre_norm_mul_fracta_24) ,
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.fractb_i(pre_norm_mul_fractb_24) ,
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.fractb_i(pre_norm_mul_fractb_24) ,
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.signa_i(s_opa_i[31]),
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.signa_i(s_opa_i[31]),
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.signb_i(s_opb_i[31]),
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.signb_i(s_opb_i[31]),
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.start_i(s_start_i) ,
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.start_i(s_start_i) ,
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.fract_o(serial_mul_fract_48) ,
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.fract_o(serial_mul_fract_48) ,
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.sign_o(serial_mul_sign) ,
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.sign_o(serial_mul_sign) ,
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.ready_o()
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.ready_o()
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);
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);
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|
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// Serial or parallel multiplier will be chosen depending on constant
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// Serial or parallel multiplier will be chosen depending on constant
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// MUL_SERIAL
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// MUL_SERIAL
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assign mul_fract_48 = MUL_SERIAL ? serial_mul_fract_48 : mul_24_fract_48;
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assign mul_fract_48 = MUL_SERIAL ? serial_mul_fract_48 : mul_24_fract_48;
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assign mul_sign = MUL_SERIAL ? serial_mul_sign : mul_24_sign;
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assign mul_sign = MUL_SERIAL ? serial_mul_sign : mul_24_sign;
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|
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or1200_fpu_post_norm_mul fpu_post_norm_mul
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or1200_fpu_post_norm_mul fpu_post_norm_mul
|
(
|
(
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.clk_i(clk_i) ,
|
.clk_i(clk_i) ,
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.opa_i(s_opa_i) ,
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.opa_i(s_opa_i) ,
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.opb_i(s_opb_i) ,
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.opb_i(s_opb_i) ,
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.exp_10_i(pre_norm_mul_exp_10) ,
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.exp_10_i(pre_norm_mul_exp_10) ,
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.fract_48_i(mul_fract_48) , // Parallel multiplier input
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.fract_48_i(mul_fract_48) , // Parallel multiplier input
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.sign_i(mul_sign) , // Parallel multiplier input
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.sign_i(mul_sign) , // Parallel multiplier input
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.rmode_i(s_rmode_i) ,
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.rmode_i(s_rmode_i) ,
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.output_o(post_norm_mul_output) ,
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.output_o(post_norm_mul_output) ,
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.ine_o(post_norm_mul_ine)
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.ine_o(post_norm_mul_ine)
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);
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);
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|
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////***Division units***
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////***Division units***
|
|
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or1200_fpu_pre_norm_div fpu_pre_norm_div
|
or1200_fpu_pre_norm_div fpu_pre_norm_div
|
(
|
(
|
.clk_i(clk_i) ,
|
.clk_i(clk_i) ,
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.opa_i(s_opa_i) ,
|
.opa_i(s_opa_i) ,
|
.opb_i(s_opb_i) ,
|
.opb_i(s_opb_i) ,
|
.exp_10_o(pre_norm_div_exp) ,
|
.exp_10_o(pre_norm_div_exp) ,
|
.dvdnd_50_o(pre_norm_div_dvdnd) ,
|
.dvdnd_50_o(pre_norm_div_dvdnd) ,
|
.dvsor_27_o(pre_norm_div_dvsor) );
|
.dvsor_27_o(pre_norm_div_dvsor) );
|
|
|
or1200_fpu_div fpu_div
|
or1200_fpu_div fpu_div
|
(
|
(
|
.clk_i(clk_i) ,
|
.clk_i(clk_i) ,
|
.dvdnd_i(pre_norm_div_dvdnd) ,
|
.dvdnd_i(pre_norm_div_dvdnd) ,
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.dvsor_i(pre_norm_div_dvsor) ,
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.dvsor_i(pre_norm_div_dvsor) ,
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.sign_dvd_i(s_opa_i[31]),
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.sign_dvd_i(s_opa_i[31]),
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.sign_div_i(s_opb_i[31]),
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.sign_div_i(s_opb_i[31]),
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.start_i(s_start_i) ,
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.start_i(s_start_i) ,
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.ready_o() ,
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.ready_o() ,
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.qutnt_o(serial_div_qutnt) ,
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.qutnt_o(serial_div_qutnt) ,
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.rmndr_o(serial_div_rmndr) ,
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.rmndr_o(serial_div_rmndr) ,
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.sign_o(serial_div_sign) ,
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.sign_o(serial_div_sign) ,
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.div_zero_o(serial_div_div_zero) );
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.div_zero_o(serial_div_div_zero) );
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|
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or1200_fpu_post_norm_div fpu_post_norm_div
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or1200_fpu_post_norm_div fpu_post_norm_div
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(
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(
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.clk_i(clk_i) ,
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.clk_i(clk_i) ,
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.opa_i(s_opa_i) ,
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.opa_i(s_opa_i) ,
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.opb_i(s_opb_i) ,
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.opb_i(s_opb_i) ,
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.qutnt_i(serial_div_qutnt) ,
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.qutnt_i(serial_div_qutnt) ,
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.rmndr_i(serial_div_rmndr) ,
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.rmndr_i(serial_div_rmndr) ,
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.exp_10_i(pre_norm_div_exp) ,
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.exp_10_i(pre_norm_div_exp) ,
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.sign_i(serial_div_sign) ,
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.sign_i(serial_div_sign) ,
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.rmode_i(s_rmode_i) ,
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.rmode_i(s_rmode_i) ,
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.output_o(post_norm_div_output) ,
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.output_o(post_norm_div_output) ,
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.ine_o(post_norm_div_ine) );
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.ine_o(post_norm_div_ine) );
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//////////////////////////////////////////////////////////////////-
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//////////////////////////////////////////////////////////////////-
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// Input Registers
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// Input Registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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s_opa_i <= opa_i;
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s_opa_i <= opa_i;
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s_opb_i <= opb_i;
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s_opb_i <= opb_i;
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s_fpu_op_i <= fpu_op_i;
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s_fpu_op_i <= fpu_op_i;
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s_rmode_i <= rmode_i;
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s_rmode_i <= rmode_i;
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s_start_i <= start_i;
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s_start_i <= start_i;
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end
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end
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// Output registers
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// Output registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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output_o <= s_output_o;
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output_o <= s_output_o;
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ine_o <= s_ine_o;
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ine_o <= s_ine_o;
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overflow_o <= s_overflow_o;
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overflow_o <= s_overflow_o;
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underflow_o <= s_underflow_o;
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underflow_o <= s_underflow_o;
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div_zero_o <= s_div_zero_o & !s_infa;
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div_zero_o <= s_div_zero_o & !s_infa;
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inf_o <= s_inf_o;
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inf_o <= s_inf_o;
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zero_o <= s_zero_o;
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zero_o <= s_zero_o;
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qnan_o <= s_qnan_o;
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qnan_o <= s_qnan_o;
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snan_o <= s_snan_o;
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snan_o <= s_snan_o;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (s_start_i) begin
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if (s_start_i) begin
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s_state <= t_state_busy;
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s_state <= t_state_busy;
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s_count <= 0;
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s_count <= 0;
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end
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end
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else if (s_state == t_state_busy) begin
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else if (s_state == t_state_busy) begin
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// Ready cases
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// Ready cases
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if (((s_count == 6) & ((fpu_op_i==3'd0) | (fpu_op_i==3'd1))) |
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if (((s_count == 6) & ((fpu_op_i==3'd0) | (fpu_op_i==3'd1))) |
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((s_count==MUL_COUNT) & (fpu_op_i==3'd2)) |
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((s_count==MUL_COUNT) & (fpu_op_i==3'd2)) |
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((s_count==33) & (fpu_op_i==3'd3)))
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((s_count==33) & (fpu_op_i==3'd3)))
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begin
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begin
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s_state <= t_state_waiting;
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s_state <= t_state_waiting;
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ready_o <= 1;
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ready_o <= 1;
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s_count <= 0;
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s_count <= 0;
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end
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end
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else
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else
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s_count <= s_count + 1;
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s_count <= s_count + 1;
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end // if (s_state == t_state_busy)
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end // if (s_state == t_state_busy)
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else begin
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else begin
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s_state <= t_state_waiting;
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s_state <= t_state_waiting;
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ready_o <= 0;
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ready_o <= 0;
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end // else: !if(s_state == t_state_busy)
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end // else: !if(s_state == t_state_busy)
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end // else: !if(s_start_i)
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end // else: !if(s_start_i)
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|
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//// Output Multiplexer
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//// Output Multiplexer
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always @(posedge clk_i)
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always @(posedge clk_i)
|
begin
|
begin
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case(fpu_op_i)
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case(fpu_op_i)
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3'd0,
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3'd0,
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3'd1: begin
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3'd1: begin
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s_output1 <= postnorm_addsub_output_o;
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s_output1 <= postnorm_addsub_output_o;
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s_ine_o <= postnorm_addsub_ine_o;
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s_ine_o <= postnorm_addsub_ine_o;
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end
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end
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3'd2: begin
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3'd2: begin
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s_output1 <= post_norm_mul_output;
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s_output1 <= post_norm_mul_output;
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s_ine_o <= post_norm_mul_ine;
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s_ine_o <= post_norm_mul_ine;
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end
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end
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3'd3: begin
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3'd3: begin
|
s_output1 <= post_norm_div_output;
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s_output1 <= post_norm_div_output;
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s_ine_o <= post_norm_div_ine;
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s_ine_o <= post_norm_div_ine;
|
end
|
end
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// 3'd4: begin
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// 3'd4: begin
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// s_output1 <= post_norm_sqrt_output;
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// s_output1 <= post_norm_sqrt_output;
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// s_ine_o <= post_norm_sqrt_ine_o;
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// s_ine_o <= post_norm_sqrt_ine_o;
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// end
|
// end
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default: begin
|
default: begin
|
s_output1 <= 0;
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s_output1 <= 0;
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s_ine_o <= 0;
|
s_ine_o <= 0;
|
end
|
end
|
endcase // case (fpu_op_i)
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endcase // case (fpu_op_i)
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end // always @ (posedge clk_i)
|
end // always @ (posedge clk_i)
|
|
|
// Infinte exponent
|
// Infinte exponent
|
assign s_infa = &s_opa_i[30:23];
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assign s_infa = &s_opa_i[30:23];
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assign s_infb = &s_opb_i[30:23];
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assign s_infb = &s_opb_i[30:23];
|
|
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always @*
|
always @*
|
begin
|
begin
|
if (s_rmode_i==2'd0 | s_div_zero_o | s_infa | s_infb | s_qnan_o |
|
if (s_rmode_i==2'd0 | s_div_zero_o | s_infa | s_infb | s_qnan_o |
|
s_qnan_o) // Round to nearest even
|
s_qnan_o) // Round to nearest even
|
s_output_o <= s_output1;
|
s_output_o = s_output1;
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else if (s_rmode_i==2'd1 & (&s_output1[30:23]))
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else if (s_rmode_i==2'd1 & (&s_output1[30:23]))
|
// In round-to-zero: the sum of two non-infinity operands is never
|
// In round-to-zero: the sum of two non-infinity operands is never
|
// infinity,even if an overflow occures
|
// infinity,even if an overflow occures
|
s_output_o <= {s_output1[31], 31'b1111111_01111111_11111111_11111111};
|
s_output_o = {s_output1[31], 31'b1111111_01111111_11111111_11111111};
|
else if (s_rmode_i==2'd2 & (&s_output1[31:23]))
|
else if (s_rmode_i==2'd2 & (&s_output1[31:23]))
|
// In round-up: the sum of two non-infinity operands is never
|
// In round-up: the sum of two non-infinity operands is never
|
// negative infinity,even if an overflow occures
|
// negative infinity,even if an overflow occures
|
s_output_o <= {32'b11111111_01111111_11111111_11111111};
|
s_output_o = {32'b11111111_01111111_11111111_11111111};
|
else if (s_rmode_i==2'd3) begin
|
else if (s_rmode_i==2'd3) begin
|
if (((s_fpu_op_i==3'd0) | (s_fpu_op_i==3'd1)) & s_zero_o &
|
if (((s_fpu_op_i==3'd0) | (s_fpu_op_i==3'd1)) & s_zero_o &
|
(s_opa_i[31] | (s_fpu_op_i[0] ^ s_opb_i[31])))
|
(s_opa_i[31] | (s_fpu_op_i[0] ^ s_opb_i[31])))
|
// In round-down: a-a= -0
|
// In round-down: a-a= -0
|
s_output_o <= {1'b1,s_output1[30:0]};
|
s_output_o = {1'b1,s_output1[30:0]};
|
else if (s_output1[31:23]==9'b0_11111111)
|
else if (s_output1[31:23]==9'b0_11111111)
|
s_output_o <= 32'b01111111011111111111111111111111;
|
s_output_o = 32'b01111111011111111111111111111111;
|
else
|
else
|
s_output_o <= s_output1;
|
s_output_o = s_output1;
|
end
|
end
|
else
|
else
|
s_output_o <= s_output1;
|
s_output_o = s_output1;
|
end // always @ *
|
end // always @ *
|
|
|
// Exception generation
|
// Exception generation
|
assign s_underflow_o = (s_output1[30:23]==8'h00) & s_ine_o;
|
assign s_underflow_o = (s_output1[30:23]==8'h00) & s_ine_o;
|
assign s_overflow_o = (s_output1[30:23]==8'hff) & s_ine_o;
|
assign s_overflow_o = (s_output1[30:23]==8'hff) & s_ine_o;
|
assign s_div_zero_o = serial_div_div_zero & fpu_op_i==3'd3;
|
assign s_div_zero_o = serial_div_div_zero & fpu_op_i==3'd3;
|
assign s_inf_o = s_output1[31:23]==8'hff & !(s_qnan_o | s_snan_o);
|
assign s_inf_o = s_output1[30:23]==8'hff & !(s_qnan_o | s_snan_o);
|
assign s_zero_o = !(|s_output1[30:0]);
|
assign s_zero_o = !(|s_output1[30:0]);
|
assign s_qnan_o = s_output1[30:0]==QNAN;
|
assign s_qnan_o = s_output1[30:0]==QNAN;
|
assign s_snan_o = s_output1[30:0]==SNAN;
|
assign s_snan_o = s_output1[30:0]==SNAN;
|
|
|
endmodule // or1200_fpu_arith
|
endmodule // or1200_fpu_arith
|
|
|
|
|
|
|
