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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_post_norm_mul.v] - Diff between revs 258 and 364

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Rev 258 Rev 364
Line 137... Line 137...
   assign s_carry = s_fract_48_i[47];
   assign s_carry = s_fract_48_i[47];
 
 
 
 
   always @(posedge clk_i)
   always @(posedge clk_i)
     if (!s_fract_48_i[47])
     if (!s_fract_48_i[47])
       casex(s_fract_48_i[46:1])        // synopsys full_case parallel_case
       casez(s_fract_48_i[46:1])        // synopsys full_case parallel_case
         46'b1?????????????????????????????????????????????: s_zeros <=  0;
         46'b1?????????????????????????????????????????????: s_zeros <=  0;
         46'b01????????????????????????????????????????????: s_zeros <=  1;
         46'b01????????????????????????????????????????????: s_zeros <=  1;
         46'b001???????????????????????????????????????????: s_zeros <=  2;
         46'b001???????????????????????????????????????????: s_zeros <=  2;
         46'b0001??????????????????????????????????????????: s_zeros <=  3;
         46'b0001??????????????????????????????????????????: s_zeros <=  3;
         46'b00001?????????????????????????????????????????: s_zeros <=  4;
         46'b00001?????????????????????????????????????????: s_zeros <=  4;
Line 191... Line 191...
     else
     else
       s_zeros <= 0;
       s_zeros <= 0;
 
 
 
 
   always @(posedge clk_i)
   always @(posedge clk_i)
     casex(s_fract_48_i) // synopsys full_case parallel_case
     casez(s_fract_48_i) // synopsys full_case parallel_case
       48'b???????????????????????????????????????????????1: s_r_zeros <=  0;
       48'b???????????????????????????????????????????????1: s_r_zeros <=  0;
       48'b??????????????????????????????????????????????10: s_r_zeros <=  1;
       48'b??????????????????????????????????????????????10: s_r_zeros <=  1;
       48'b?????????????????????????????????????????????100: s_r_zeros <=  2;
       48'b?????????????????????????????????????????????100: s_r_zeros <=  2;
       48'b????????????????????????????????????????????1000: s_r_zeros <=  3;
       48'b????????????????????????????????????????????1000: s_r_zeros <=  3;
       48'b???????????????????????????????????????????10000: s_r_zeros <=  4;
       48'b???????????????????????????????????????????10000: s_r_zeros <=  4;
Line 269... Line 269...
   always @(posedge clk_i)
   always @(posedge clk_i)
     begin
     begin
        if ((s_exp_10a[9] | !(|s_exp_10a)))
        if ((s_exp_10a[9] | !(|s_exp_10a)))
          s_expo1 <= 9'd1;
          s_expo1 <= 9'd1;
        else if (s_exp_10b[9] | !(|s_exp_10b))
        else if (s_exp_10b[9] | !(|s_exp_10b))
          s_expo1 <= 1'd1;
          s_expo1 <= 9'd1;
        else if (s_exp_10b[8])
        else if (s_exp_10b[8])
          s_expo1 <= 9'b011111111;
          s_expo1 <= 9'b011111111;
        else
        else
          s_expo1 <= s_exp_10b[8:0];
          s_expo1 <= s_exp_10b[8:0];
 
 

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