URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 136...	Line 136...
assign icpu_tag_o = `OR1200_ITAG_NI;	assign icpu_tag_o = `OR1200_ITAG_NI;

`//`	`//`
`// genpc_freeze_r`	`// genpc_freeze_r`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`genpc_refetch_r <= 1'b0;`	`genpc_refetch_r <= 1'b0;`
`else if (genpc_refetch)`	`else if (genpc_refetch)`
`genpc_refetch_r <= 1'b1;`	`genpc_refetch_r <= 1'b1;`
`else`	`else`
`genpc_refetch_r <= 1'b0;`	`genpc_refetch_r <= 1'b0;`
Line 253...	Line 253...
`end`	`end`

`//`	`//`
`// PC register`	`// PC register`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`// default value`	`// default value`
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; // jb	pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; // jb
`pcreg_select <= 1'b1;// select async. value due to reset state`	`pcreg_select <= 1'b1;// select async. value due to reset state`
`end`	`end`
`// selected value (different from default) is written into FF after`	`// selected value (different from default) is written into FF after`
`// reset state`	`// reset state`