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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Diff between revs 813 and 847

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Rev 813 Rev 847
Line 62... Line 62...
        // Internal i/f
        // Internal i/f
        pre_branch_op, branch_op, except_type, except_prefix,
        pre_branch_op, branch_op, except_type, except_prefix,
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
        flag, flagforw, ex_branch_taken, except_start,
        flag, flagforw, ex_branch_taken, except_start,
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, no_more_dslot
        genpc_freeze, no_more_dslot, lsu_stall
);
);
 
 
//
//
// I/O
// I/O
//
//
Line 106... Line 106...
input   [31:0]                   spr_dat_i;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_refetch;
input                           genpc_freeze;
input                           genpc_freeze;
input                           no_more_dslot;
input                           no_more_dslot;
 
input                           lsu_stall;
 
 
parameter boot_adr = `OR1200_BOOT_ADR;
parameter boot_adr = `OR1200_BOOT_ADR;
//
//
// Internal wires and regs
// Internal wires and regs
//
//
Line 118... Line 119...
reg     [31:2]                  pcreg;
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg     [31:0]                   pc;
// Set in event of jump or taken branch   
// Set in event of jump or taken branch   
reg                             ex_branch_taken;
reg                             ex_branch_taken;
reg                             genpc_refetch_r;
reg                             genpc_refetch_r;
 
reg                             wait_lsu;
 
 
   //
   //
   // Address of insn to be fecthed
   // Address of insn to be fecthed
   //
   //
   assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
   assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
Line 129... Line 131...
                       icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
                       icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
 
 
   //
   //
   // Control access to IC subsystem
   // Control access to IC subsystem
   //
   //
   assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
   assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i) | wait_lsu);
   assign icpu_sel_o = 4'b1111;
   assign icpu_sel_o = 4'b1111;
   assign icpu_tag_o = `OR1200_ITAG_NI;
   assign icpu_tag_o = `OR1200_ITAG_NI;
 
 
   //
   //
 
   // wait_lsu
 
   //
 
   always @(posedge clk or `OR1200_RST_EVENT rst)
 
     if (rst == `OR1200_RST_VALUE)
 
       wait_lsu <=  1'b0;
 
     else if (!wait_lsu & |pre_branch_op & lsu_stall)
 
       wait_lsu <=  1'b1;
 
     else if (wait_lsu & ~|pre_branch_op)
 
       wait_lsu <=  1'b0;
 
 
 
   //
   // genpc_freeze_r
   // genpc_freeze_r
   //
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
     if (rst == `OR1200_RST_VALUE)
       genpc_refetch_r <=  1'b0;
       genpc_refetch_r <=  1'b0;

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