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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Diff between revs 481 and 679

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Rev 481 Rev 679
Line 73... Line 73...
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
);
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
parameter boot_adr = `OR1200_BOOT_ADR;
 
 
//
//
// I/O
// I/O
//
//
 
 
Line 146... Line 147...
wire                            itlb_done;
wire                            itlb_done;
wire                            fault;
wire                            fault;
wire                            miss;
wire                            miss;
wire                            page_cross;
wire                            page_cross;
reg     [31:0]                   icpu_adr_default;
reg     [31:0]                   icpu_adr_default;
wire    [31:0]                   icpu_adr_boot;
 
reg                             icpu_adr_select;
reg                             icpu_adr_select;
reg             [31:0]           icpu_adr_o;
reg             [31:0]           icpu_adr_o;
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`ifdef OR1200_NO_IMMU
`else
`else
Line 174... Line 174...
 
 
//
//
// icpu_adr_o
// icpu_adr_o
//
//
`ifdef OR1200_REGISTERED_OUTPUTS
`ifdef OR1200_REGISTERED_OUTPUTS
 
wire    [31:0]                   icpu_adr_boot = boot_adr;
 
 
always @(`OR1200_RST_EVENT rst or posedge clk)
always @(`OR1200_RST_EVENT rst or posedge clk)
        // default value 
        // default value 
        if (rst == `OR1200_RST_VALUE) begin
        if (rst == `OR1200_RST_VALUE) begin
                // select async. value due to reset state
                // select async. value due to reset state
                icpu_adr_default <=  32'h0000_0100;
                icpu_adr_default <=  32'h0000_0100;
Line 197... Line 199...
 
 
// select async. value for boot address after reset - PC jumps to the address 
// select async. value for boot address after reset - PC jumps to the address 
// selected after boot! 
// selected after boot! 
   //assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : 
   //assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : 
   // `OR1200_EXCEPT_EPH0_P), 12'h100} ;
   // `OR1200_EXCEPT_EPH0_P), 12'h100} ;
   assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
 
 
 
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
        if (icpu_adr_select)
        if (icpu_adr_select)
                // async. value is selected due to reset state 
                // async. value is selected due to reset state 
                icpu_adr_o = icpu_adr_boot ;
                icpu_adr_o = icpu_adr_boot ;

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