//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Instruction MMU top level ////
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//// OR1200's Instruction MMU top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all IMMU blocks. ////
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//// Instantiation of all IMMU blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - cache inhibit ////
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//// - cache inhibit ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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//
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//
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// Insn MMU
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// Insn MMU
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//
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//
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|
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module or1200_immu_top(
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module or1200_immu_top(
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// Rst and clk
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// Rst and clk
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clk, rst,
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clk, rst,
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|
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// CPU i/f
|
// CPU i/f
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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|
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// SR Interface
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// SR Interface
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boot_adr_sel_i,
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boot_adr_sel_i,
|
|
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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|
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
|
|
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// QMEM i/f
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// QMEM i/f
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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);
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);
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|
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter boot_adr = `OR1200_BOOT_ADR;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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|
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//
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//
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// CPU I/F
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// CPU I/F
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//
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//
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input ic_en;
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input ic_en;
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input immu_en;
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input immu_en;
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input supv;
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input supv;
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input [aw-1:0] icpu_adr_i;
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input [aw-1:0] icpu_adr_i;
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input icpu_cycstb_i;
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input icpu_cycstb_i;
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output [aw-1:0] icpu_adr_o;
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output [aw-1:0] icpu_adr_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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output icpu_rty_o;
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output icpu_rty_o;
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output icpu_err_o;
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output icpu_err_o;
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|
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//
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//
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// SR Interface
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// SR Interface
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//
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//
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input boot_adr_sel_i;
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input boot_adr_sel_i;
|
|
|
//
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//
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// SPR access
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// SPR access
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//
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//
|
input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [aw-1:0] spr_addr;
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input [aw-1:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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|
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
|
//
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// RAM BIST
|
// RAM BIST
|
//
|
//
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input mbist_si_i;
|
input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
|
output mbist_so_o;
|
`endif
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`endif
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|
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//
|
//
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// IC I/F
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// IC I/F
|
//
|
//
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input qmemimmu_rty_i;
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input qmemimmu_rty_i;
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input qmemimmu_err_i;
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input qmemimmu_err_i;
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input [3:0] qmemimmu_tag_i;
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input [3:0] qmemimmu_tag_i;
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output [aw-1:0] qmemimmu_adr_o;
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output [aw-1:0] qmemimmu_adr_o;
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output qmemimmu_cycstb_o;
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output qmemimmu_cycstb_o;
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output qmemimmu_ci_o;
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output qmemimmu_ci_o;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
|
//
|
//
|
wire itlb_spr_access;
|
wire itlb_spr_access;
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wire [31:`OR1200_IMMU_PS] itlb_ppn;
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wire [31:`OR1200_IMMU_PS] itlb_ppn;
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wire itlb_hit;
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wire itlb_hit;
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wire itlb_uxe;
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wire itlb_uxe;
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wire itlb_sxe;
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wire itlb_sxe;
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wire [31:0] itlb_dat_o;
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wire [31:0] itlb_dat_o;
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wire itlb_en;
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wire itlb_en;
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wire itlb_ci;
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wire itlb_ci;
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wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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wire page_cross;
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wire page_cross;
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reg [31:0] icpu_adr_default;
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reg [31:0] icpu_adr_default;
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wire [31:0] icpu_adr_boot;
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reg icpu_adr_select;
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reg icpu_adr_select;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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`else
|
`else
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reg itlb_en_r;
|
reg itlb_en_r;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_scnd_clk;
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reg dis_spr_access_scnd_clk;
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`endif
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`endif
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|
|
//
|
//
|
// Implemented bits inside match and translate registers
|
// Implemented bits inside match and translate registers
|
//
|
//
|
// itlbwYmrX: vpn 31-10 v 0
|
// itlbwYmrX: vpn 31-10 v 0
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// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
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// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
|
//
|
//
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// itlb memory width:
|
// itlb memory width:
|
// 19 bits for ppn
|
// 19 bits for ppn
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// 13 bits for vpn
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// 13 bits for vpn
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// 1 bit for valid
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// 1 bit for valid
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// 2 bits for protection
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// 2 bits for protection
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// 1 bit for cache inhibit
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// 1 bit for cache inhibit
|
|
|
//
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//
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// icpu_adr_o
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// icpu_adr_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
wire [31:0] icpu_adr_boot = boot_adr;
|
|
|
always @(`OR1200_RST_EVENT rst or posedge clk)
|
always @(`OR1200_RST_EVENT rst or posedge clk)
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// default value
|
// default value
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if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
// select async. value due to reset state
|
// select async. value due to reset state
|
icpu_adr_default <= 32'h0000_0100;
|
icpu_adr_default <= 32'h0000_0100;
|
icpu_adr_select <= 1'b1;
|
icpu_adr_select <= 1'b1;
|
end
|
end
|
// selected value (different from default) is written
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// selected value (different from default) is written
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// into FF after reset state
|
// into FF after reset state
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else if (icpu_adr_select) begin
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else if (icpu_adr_select) begin
|
// dynamic value can only be assigned to FF out of reset!
|
// dynamic value can only be assigned to FF out of reset!
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icpu_adr_default <= icpu_adr_boot;
|
icpu_adr_default <= icpu_adr_boot;
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// select FF value
|
// select FF value
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icpu_adr_select <= 1'b0;
|
icpu_adr_select <= 1'b0;
|
end
|
end
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else begin
|
else begin
|
icpu_adr_default <= icpu_adr_i;
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icpu_adr_default <= icpu_adr_i;
|
end
|
end
|
|
|
// select async. value for boot address after reset - PC jumps to the address
|
// select async. value for boot address after reset - PC jumps to the address
|
// selected after boot!
|
// selected after boot!
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
|
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
|
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
|
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
|
assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
|
|
|
|
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
|
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
|
if (icpu_adr_select)
|
if (icpu_adr_select)
|
// async. value is selected due to reset state
|
// async. value is selected due to reset state
|
icpu_adr_o = icpu_adr_boot ;
|
icpu_adr_o = icpu_adr_boot ;
|
else
|
else
|
// FF value is selected 2nd clock after reset state
|
// FF value is selected 2nd clock after reset state
|
icpu_adr_o = icpu_adr_default ;
|
icpu_adr_o = icpu_adr_default ;
|
`else
|
`else
|
Unsupported !!!
|
Unsupported !!!
|
`endif
|
`endif
|
|
|
//
|
//
|
// Page cross
|
// Page cross
|
//
|
//
|
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
|
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
|
//
|
//
|
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
|
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
|
|
|
//
|
//
|
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
|
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
|
// one clock cycle after offset part.
|
// one clock cycle after offset part.
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
|
icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
|
else
|
else
|
icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
|
icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
|
|
|
`ifdef OR1200_NO_IMMU
|
`ifdef OR1200_NO_IMMU
|
|
|
//
|
//
|
// Put all outputs in inactive state
|
// Put all outputs in inactive state
|
//
|
//
|
assign spr_dat_o = 32'h00000000;
|
assign spr_dat_o = 32'h00000000;
|
assign qmemimmu_adr_o = icpu_adr_i;
|
assign qmemimmu_adr_o = icpu_adr_i;
|
assign icpu_tag_o = qmemimmu_tag_i;
|
assign icpu_tag_o = qmemimmu_tag_i;
|
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
|
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
|
assign icpu_rty_o = qmemimmu_rty_i;
|
assign icpu_rty_o = qmemimmu_rty_i;
|
assign icpu_err_o = qmemimmu_err_i;
|
assign icpu_err_o = qmemimmu_err_i;
|
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
|
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
assign mbist_so_o = mbist_si_i;
|
assign mbist_so_o = mbist_si_i;
|
`endif
|
`endif
|
`else
|
`else
|
|
|
//
|
//
|
// ITLB SPR access
|
// ITLB SPR access
|
//
|
//
|
// 1200 - 12FF itlbmr w0
|
// 1200 - 12FF itlbmr w0
|
// 1200 - 123F itlbmr w0 [63:0]
|
// 1200 - 123F itlbmr w0 [63:0]
|
//
|
//
|
// 1300 - 13FF itlbtr w0
|
// 1300 - 13FF itlbtr w0
|
// 1300 - 133F itlbtr w0 [63:0]
|
// 1300 - 133F itlbtr w0 [63:0]
|
//
|
//
|
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
|
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
|
|
|
//
|
//
|
// Disable ITLB SPR access
|
// Disable ITLB SPR access
|
//
|
//
|
// This flops are used to mask ITLB miss/fault exception
|
// This flops are used to mask ITLB miss/fault exception
|
// during first & second clock cycles of accessing ITLB SPR. In
|
// during first & second clock cycles of accessing ITLB SPR. In
|
// subsequent clock cycles it is assumed that ITLB SPR
|
// subsequent clock cycles it is assumed that ITLB SPR
|
// access was accomplished and that normal instruction fetching
|
// access was accomplished and that normal instruction fetching
|
// can proceed.
|
// can proceed.
|
//
|
//
|
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
|
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
|
// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
|
// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
|
// icpu_rty_o clears it.
|
// icpu_rty_o clears it.
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
dis_spr_access_frst_clk <= 1'b0;
|
dis_spr_access_frst_clk <= 1'b0;
|
else if (!icpu_rty_o)
|
else if (!icpu_rty_o)
|
dis_spr_access_frst_clk <= 1'b0;
|
dis_spr_access_frst_clk <= 1'b0;
|
else if (spr_cs)
|
else if (spr_cs)
|
dis_spr_access_frst_clk <= 1'b1;
|
dis_spr_access_frst_clk <= 1'b1;
|
|
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
dis_spr_access_scnd_clk <= 1'b0;
|
dis_spr_access_scnd_clk <= 1'b0;
|
else if (!icpu_rty_o)
|
else if (!icpu_rty_o)
|
dis_spr_access_scnd_clk <= 1'b0;
|
dis_spr_access_scnd_clk <= 1'b0;
|
else if (dis_spr_access_frst_clk)
|
else if (dis_spr_access_frst_clk)
|
dis_spr_access_scnd_clk <= 1'b1;
|
dis_spr_access_scnd_clk <= 1'b1;
|
|
|
//
|
//
|
// Tags:
|
// Tags:
|
//
|
//
|
// OR1200_ITAG_TE - TLB miss Exception
|
// OR1200_ITAG_TE - TLB miss Exception
|
// OR1200_ITAG_PE - Page fault Exception
|
// OR1200_ITAG_PE - Page fault Exception
|
//
|
//
|
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
|
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
|
|
|
//
|
//
|
// icpu_rty_o
|
// icpu_rty_o
|
//
|
//
|
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
|
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
|
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
|
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
|
assign icpu_rty_o = qmemimmu_rty_i;
|
assign icpu_rty_o = qmemimmu_rty_i;
|
|
|
//
|
//
|
// icpu_err_o
|
// icpu_err_o
|
//
|
//
|
assign icpu_err_o = miss | fault | qmemimmu_err_i;
|
assign icpu_err_o = miss | fault | qmemimmu_err_i;
|
|
|
//
|
//
|
// Assert itlb_en_r after one clock cycle and when there is no
|
// Assert itlb_en_r after one clock cycle and when there is no
|
// ITLB SPR access
|
// ITLB SPR access
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
itlb_en_r <= 1'b0;
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itlb_en_r <= 1'b0;
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else
|
else
|
itlb_en_r <= itlb_en & ~itlb_spr_access;
|
itlb_en_r <= itlb_en & ~itlb_spr_access;
|
|
|
//
|
//
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// ITLB lookup successful
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// ITLB lookup successful
|
//
|
//
|
assign itlb_done = itlb_en_r & ~page_cross;
|
assign itlb_done = itlb_en_r & ~page_cross;
|
|
|
//
|
//
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// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
|
// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
|
// wrong with translation. If IC is disabled, use delayed signals.
|
// wrong with translation. If IC is disabled, use delayed signals.
|
//
|
//
|
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
|
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
|
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
|
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
|
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
|
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
|
|
|
//
|
//
|
// Cache Inhibit
|
// Cache Inhibit
|
//
|
//
|
// Cache inhibit is not really needed for instruction memory subsystem.
|
// Cache inhibit is not really needed for instruction memory subsystem.
|
// If we would doq it, we would doq it like this.
|
// If we would doq it, we would doq it like this.
|
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
|
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
|
// However this causes an async combinatorial loop so we stick to
|
// However this causes an async combinatorial loop so we stick to
|
// no cache inhibit.
|
// no cache inhibit.
|
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
|
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
|
// Cache inhibit without an async combinatorial loop
|
// Cache inhibit without an async combinatorial loop
|
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
|
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
|
|
|
|
|
//
|
//
|
// Physical address is either translated virtual address or
|
// Physical address is either translated virtual address or
|
// simply equal when IMMU is disabled
|
// simply equal when IMMU is disabled
|
//
|
//
|
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
|
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
|
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
|
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
|
|
|
reg [31:0] spr_dat_reg;
|
reg [31:0] spr_dat_reg;
|
//
|
//
|
// Output to SPRS unit
|
// Output to SPRS unit
|
//
|
//
|
// spr_dat_o is registered on the 1st clock of spr read
|
// spr_dat_o is registered on the 1st clock of spr read
|
// so itlb can continue with process during execution of mfspr.
|
// so itlb can continue with process during execution of mfspr.
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
spr_dat_reg <= 32'h0000_0000;
|
spr_dat_reg <= 32'h0000_0000;
|
else if (spr_cs & !dis_spr_access_scnd_clk)
|
else if (spr_cs & !dis_spr_access_scnd_clk)
|
spr_dat_reg <= itlb_dat_o;
|
spr_dat_reg <= itlb_dat_o;
|
|
|
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
|
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
|
|
|
//
|
//
|
// Page fault exception logic
|
// Page fault exception logic
|
//
|
//
|
assign fault = itlb_done &
|
assign fault = itlb_done &
|
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
|
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
|
|
|
//
|
//
|
// TLB Miss exception logic
|
// TLB Miss exception logic
|
//
|
//
|
assign miss = itlb_done & !itlb_hit;
|
assign miss = itlb_done & !itlb_hit;
|
|
|
//
|
//
|
// ITLB Enable
|
// ITLB Enable
|
//
|
//
|
assign itlb_en = immu_en & icpu_cycstb_i;
|
assign itlb_en = immu_en & icpu_cycstb_i;
|
|
|
//
|
//
|
// Instantiation of ITLB
|
// Instantiation of ITLB
|
//
|
//
|
or1200_immu_tlb or1200_immu_tlb(
|
or1200_immu_tlb or1200_immu_tlb(
|
// Rst and clk
|
// Rst and clk
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
|
|
// I/F for translation
|
// I/F for translation
|
.tlb_en(itlb_en),
|
.tlb_en(itlb_en),
|
.vaddr(icpu_adr_i),
|
.vaddr(icpu_adr_i),
|
.hit(itlb_hit),
|
.hit(itlb_hit),
|
.ppn(itlb_ppn),
|
.ppn(itlb_ppn),
|
.uxe(itlb_uxe),
|
.uxe(itlb_uxe),
|
.sxe(itlb_sxe),
|
.sxe(itlb_sxe),
|
.ci(itlb_ci),
|
.ci(itlb_ci),
|
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_si_i),
|
.mbist_si_i(mbist_si_i),
|
.mbist_so_o(mbist_so_o),
|
.mbist_so_o(mbist_so_o),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(itlb_spr_access),
|
.spr_cs(itlb_spr_access),
|
.spr_write(spr_write),
|
.spr_write(spr_write),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_i),
|
.spr_dat_i(spr_dat_i),
|
.spr_dat_o(itlb_dat_o)
|
.spr_dat_o(itlb_dat_o)
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
