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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 92...	Line 92...
`reg saved_b;`	`reg saved_b;`

`//`	`//`
`// Operand A register`	`// Operand A register`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`operand_a <= 32'd0;`	`operand_a <= 32'd0;`
`saved_a <= 1'b0;`	`saved_a <= 1'b0;`
`end else if (!ex_freeze && id_freeze && !saved_a) begin`	`end else if (!ex_freeze && id_freeze && !saved_a) begin`
`operand_a <= muxed_a;`	`operand_a <= muxed_a;`
`saved_a <= 1'b1;`	`saved_a <= 1'b1;`
Line 108...	Line 108...
`end`	`end`

`//`	`//`
`// Operand B register`	`// Operand B register`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`operand_b <= 32'd0;`	`operand_b <= 32'd0;`
`saved_b <= 1'b0;`	`saved_b <= 1'b0;`
`end else if (!ex_freeze && id_freeze && !saved_b) begin`	`end else if (!ex_freeze && id_freeze && !saved_b) begin`
`operand_b <= muxed_b;`	`operand_b <= muxed_b;`
`saved_b <= 1'b1;`	`saved_b <= 1'b1;`