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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 642 and 808

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Rev 642 Rev 808
Line 55... Line 55...
                   // Clk & Rst
                   // Clk & Rst
                   clk, rst,
                   clk, rst,
 
 
                   // Internal CPU interface
                   // Internal CPU interface
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
                   ovforw, ov_we,
                   ovforw, ov_we, dsx,
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
                   ex_spr_write,
                   ex_spr_write,
                   epcr, eear, esr, except_started,
                   epcr, eear, esr, except_started,
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
Line 97... Line 97...
   input                                cyforw;         // From ALU
   input                                cyforw;         // From ALU
   input                                cy_we;          // From ALU
   input                                cy_we;          // From ALU
   output                               carry;          // SR[CY]
   output                               carry;          // SR[CY]
   input                                ovforw;         // From ALU
   input                                ovforw;         // From ALU
   input                                ov_we;          // From ALU
   input                                ov_we;          // From ALU
 
   input                                dsx;            // From except
   input [width-1:0]                     addrbase;       // SPR base address
   input [width-1:0]                     addrbase;       // SPR base address
   input [15:0]                  addrofs;        // SPR offset
   input [15:0]                  addrofs;        // SPR offset
   input [width-1:0]                     dat_i;          // SPR write data
   input [width-1:0]                     dat_i;          // SPR write data
   input                                ex_spr_read;    // l.mfspr in EX
   input                                ex_spr_read;    // l.mfspr in EX
   input                                ex_spr_write;   // l.mtspr in EX
   input                                ex_spr_write;   // l.mtspr in EX
Line 287... Line 288...
 
 
   //
   //
   // What to write into SR
   // What to write into SR
   //
   //
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
            = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} :
            = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_EPH],dsx,1'b0} :
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
              esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
              sr[`OR1200_SR_FO:`OR1200_SR_OVE];
              sr[`OR1200_SR_FO:`OR1200_SR_OVE];
   assign to_sr[`OR1200_SR_TED]
   assign to_sr[`OR1200_SR_TED]

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