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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's interface to SPRs ////
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//// OR1200's interface to SPRs ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Decoding of SPR addresses and access to SPRs ////
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//// Decoding of SPR addresses and access to SPRs ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_sprs.v,v $
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// $Log: or1200_sprs.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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// Revision 1.11 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.9.4.1 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.9 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.8 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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// Revision 1.7 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.3 2002/01/19 09:27:49 lampret
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// SR[TEE] should be zero after reset.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.10 2001/11/12 01:45:41 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.3 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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Line 61... |
epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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boot_adr_sel_i,
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boot_adr_sel_i,
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// Floating point control register and SPR input
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fpcsr, fpcsr_we, spr_dat_fpu
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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Line 116... |
input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_mac; // Data from MAC
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input [31:0] spr_dat_mac; // Data from MAC
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input boot_adr_sel_i;
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input boot_adr_sel_i;
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input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR
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output fpcsr_we; // Write enable FPCSR
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input [31:0] spr_dat_fpu; // Data from FPU
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//
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//
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// To/from other RISC units
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// To/from other RISC units
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//
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//
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_tt; // Data from TT
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input [31:0] spr_dat_tt; // Data from TT
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wire ppc_sel; // Select for PPC
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wire ppc_sel; // Select for PPC
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wire sr_sel; // Select for SR
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wire sr_sel; // Select for SR
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wire epcr_sel; // Select for EPCR0
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wire epcr_sel; // Select for EPCR0
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wire eear_sel; // Select for EEAR0
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wire eear_sel; // Select for EEAR0
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wire esr_sel; // Select for ESR0
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wire esr_sel; // Select for ESR0
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wire fpcsr_sel; // Select for FPCSR
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wire [31:0] sys_data; // Read data from system SPRs
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wire [31:0] sys_data; // Read data from system SPRs
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wire du_access; // Debug unit access
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wire du_access; // Debug unit access
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reg [31:0] unqualified_cs; // Unqualified chip selects
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reg [31:0] unqualified_cs; // Unqualified chip selects
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wire ex_spr_write; // jb
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wire ex_spr_write; // jb
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Line 286... |
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
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assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
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assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
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assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
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assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
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assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
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assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
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assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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`ifdef OR1200_FPU_IMPLEMENTED
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assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
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`else
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assign fpcsr_sel = 0;
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`endif
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//
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//
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// Write enables for system SPRs
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// Write enables for system SPRs
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//
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//
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assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
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assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
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assign pc_we = (du_write && (npc_sel | ppc_sel));
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assign pc_we = (du_write && (npc_sel | ppc_sel));
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assign epcr_we = (spr_we && epcr_sel);
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assign epcr_we = (spr_we && epcr_sel);
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assign eear_we = (spr_we && eear_sel);
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assign eear_we = (spr_we && eear_sel);
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assign esr_we = (spr_we && esr_sel);
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assign esr_we = (spr_we && esr_sel);
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`ifdef OR1200_FPU_IMPLEMENTED
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assign fpcsr_we = (spr_we && fpcsr_sel);
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`else
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assign fpcsr_we = 0;
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`endif
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//
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//
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// Output from system SPRs
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// Output from system SPRs
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//
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//
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assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
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assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
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Line 317... |
(spr_dat_npc & {32{npc_sel}}) |
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(spr_dat_npc & {32{npc_sel}}) |
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(spr_dat_ppc & {32{ppc_sel}}) |
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(spr_dat_ppc & {32{ppc_sel}}) |
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({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
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({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
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(epcr & {32{epcr_sel}}) |
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(epcr & {32{epcr_sel}}) |
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(eear & {32{eear_sel}}) |
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(eear & {32{eear_sel}}) |
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`ifdef OR1200_FPU_IMPLEMENTED
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({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
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{32{read_spr & fpcsr_sel}}) |
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`endif
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({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
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({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
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//
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//
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// Flag alias
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// Flag alias
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//
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//
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Line 371... |
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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`ifdef OR1200_FPU_IMPLEMENTED
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spr_dat_fpu or
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`endif
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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`OR1200_SPR_GROUP_SYS:
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`OR1200_SPR_GROUP_SYS:
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to_wbmux = sys_data;
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to_wbmux = sys_data;
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`OR1200_SPR_GROUP_TT:
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`OR1200_SPR_GROUP_TT:
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Line 390... |
to_wbmux = spr_dat_dmmu;
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to_wbmux = spr_dat_dmmu;
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`OR1200_SPR_GROUP_IMMU:
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`OR1200_SPR_GROUP_IMMU:
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to_wbmux = spr_dat_immu;
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to_wbmux = spr_dat_immu;
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`OR1200_SPR_GROUP_MAC:
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`OR1200_SPR_GROUP_MAC:
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to_wbmux = spr_dat_mac;
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to_wbmux = spr_dat_mac;
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`ifdef OR1200_FPU_IMPLEMENTED
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`OR1200_SPR_GROUP_FPU:
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to_wbmux = spr_dat_fpu;
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`endif
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default: //`OR1200_SPR_GROUP_DU:
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default: //`OR1200_SPR_GROUP_DU:
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to_wbmux = spr_dat_du;
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to_wbmux = spr_dat_du;
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endcase
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endcase
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end
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end
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