| Line 97... |
Line 97... |
input [15:0] addrofs; // SPR offset
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input [15:0] addrofs; // SPR offset
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input [width-1:0] dat_i; // SPR write data
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input [width-1:0] dat_i; // SPR write data
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_write; // l.mtspr in EX
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input ex_spr_write; // l.mtspr in EX
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [width-1:0] epcr; // EPCR0
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input [width-1:0] epcr /* verilator public */; // EPCR0
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input [width-1:0] eear; // EEAR0
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input [width-1:0] eear /* verilator public */; // EEAR0
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input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
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input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
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input except_started; // Exception was started
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input except_started; // Exception was started
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output [width-1:0] to_wbmux; // For l.mfspr
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output [width-1:0] to_wbmux; // For l.mfspr
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output epcr_we; // EPCR0 write enable
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output epcr_we; // EPCR0 write enable
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output eear_we; // EEAR0 write enable
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output eear_we; // EEAR0 write enable
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output esr_we; // ESR0 write enable
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output esr_we; // ESR0 write enable
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output pc_we; // PC write enable
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output pc_we; // PC write enable
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output sr_we; // Write enable SR
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output sr_we; // Write enable SR
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output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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output [`OR1200_SR_WIDTH-1:0] sr; // SR
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output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */; // SR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_mac; // Data from MAC
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input [31:0] spr_dat_mac; // Data from MAC
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Line 356... |
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// EPH part joined together with rest of Supervision register
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// EPH part joined together with rest of Supervision register
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always @(sr_reg or sr_reg_bit_eph_muxed)
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always @(sr_reg or sr_reg_bit_eph_muxed)
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sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
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sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
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`ifdef verilator
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// Function to access various sprs (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_sr;
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// verilator public
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get_sr = sr;
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endfunction // get_sr
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function [31:0] get_epcr;
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// verilator public
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get_epcr = epcr;
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endfunction // get_epcr
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function [31:0] get_eear;
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// verilator public
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get_eear = eear;
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endfunction // get_eear
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function [31:0] get_esr;
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// verilator public
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get_esr = esr;
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endfunction // get_esr
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`endif
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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spr_dat_fpu or
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spr_dat_fpu or
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