URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 10 and 142

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 10	Rev 142
Line 60...	Line 60...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_tpram_32x32.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// Minor update:`
	`// Coding style changed.`
	`//`
	`// Revision 1.5 2005/10/19 11:37:56 jcastillo`
	`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
	`//`
`// Revision 1.4 2004/06/08 18:15:48 lampret`	`// Revision 1.4 2004/06/08 18:15:48 lampret`
`// Changed behavior of the simulation generic models`	`// Changed behavior of the simulation generic models`
`//`	`//`
`// Revision 1.3 2004/04/05 08:29:57 lampret`	`// Revision 1.3 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`	`// Merged branch_qmem into main tree.`
Line 227...	Line 234...
`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`RAMB4_S16_S16 ramb4_s16_s16_0(`	`RAMB4_S16_S16 ramb4_s16_s16_0(`
`.CLKA(clk_a),`	`.CLKA(clk_a),`
`.RSTA(rst_a),`	`.RSTA(1'b0),`
`.ADDRA(addr_a),`	`.ADDRA(addr_a),`
`.DIA(di_a[15:0]),`	`.DIA(di_a[15:0]),`
`.ENA(ce_a),`	`.ENA(ce_a),`
`.WEA(we_a),`	`.WEA(we_a),`
`.DOA(do_a[15:0]),`	`.DOA(do_a[15:0]),`

`.CLKB(clk_b),`	`.CLKB(clk_b),`
`.RSTB(rst_b),`	`.RSTB(1'b0),`
`.ADDRB(addr_b),`	`.ADDRB(addr_b),`
`.DIB(di_b[15:0]),`	`.DIB(di_b[15:0]),`
`.ENB(ce_b),`	`.ENB(ce_b),`
`.WEB(we_b),`	`.WEB(we_b),`
`.DOB(do_b[15:0])`	`.DOB(do_b[15:0])`
Line 248...	Line 255...
`//`	`//`
`// Block 1`	`// Block 1`
`//`	`//`
`RAMB4_S16_S16 ramb4_s16_s16_1(`	`RAMB4_S16_S16 ramb4_s16_s16_1(`
`.CLKA(clk_a),`	`.CLKA(clk_a),`
`.RSTA(rst_a),`	`.RSTA(1'b0),`
`.ADDRA(addr_a),`	`.ADDRA(addr_a),`
`.DIA(di_a[31:16]),`	`.DIA(di_a[31:16]),`
`.ENA(ce_a),`	`.ENA(ce_a),`
`.WEA(we_a),`	`.WEA(we_a),`
`.DOA(do_a[31:16]),`	`.DOA(do_a[31:16]),`

`.CLKB(clk_b),`	`.CLKB(clk_b),`
`.RSTB(rst_b),`	`.RSTB(1'b0),`
`.ADDRB(addr_b),`	`.ADDRB(addr_b),`
`.DIB(di_b[31:16]),`	`.DIB(di_b[31:16]),`
`.ENB(ce_b),`	`.ENB(ce_b),`
`.WEB(we_b),`	`.WEB(we_b),`
`.DOB(do_b[31:16])`	`.DOB(do_b[31:16])`
Line 278...	Line 285...
`// Added By Nir Mor`	`// Added By Nir Mor`
`//`	`//`

`RAMB16_S36_S36 ramb16_s36_s36(`	`RAMB16_S36_S36 ramb16_s36_s36(`
`.CLKA(clk_a),`	`.CLKA(clk_a),`
`.SSRA(rst_a),`	`.SSRA(1'b0),`
`.ADDRA({4'b0000,addr_a}),`	`.ADDRA({4'b0000,addr_a}),`
`.DIA(di_a),`	`.DIA(di_a),`
`.DIPA(4'h0),`	`.DIPA(4'h0),`
`.ENA(ce_a),`	`.ENA(ce_a),`
`.WEA(we_a),`	`.WEA(we_a),`
`.DOA(do_a),`	`.DOA(do_a),`
`.DOPA(),`	`.DOPA(),`

`.CLKB(clk_b),`	`.CLKB(clk_b),`
`.SSRB(rst_b),`	`.SSRB(1'b0),`
`.ADDRB({4'b0000,addr_b}),`	`.ADDRB({4'b0000,addr_b}),`
`.DIB(di_b),`	`.DIB(di_b),`
`.DIPB(4'h0),`	`.DIPB(4'h0),`
`.ENB(ce_b),`	`.ENB(ce_b),`
`.WEB(we_b),`	`.WEB(we_b),`
Line 316...	Line 323...
`.inclocken_a (ce_a),`	`.inclocken_a (ce_a),`
`.wraddress_b (addr_b),`	`.wraddress_b (addr_b),`
`.wren_a (we_a),`	`.wren_a (we_a),`
`.inclocken_b (ce_b),`	`.inclocken_b (ce_b),`
`.wren_b (we_b),`	`.wren_b (we_b),`
`.inaclr_a (rst_a),`	`.inaclr_a (1'b0),`
`.inaclr_b (rst_b),`	`.inaclr_b (1'b0),`
`.inclock_a (clk_a),`	`.inclock_a (clk_a),`
`.inclock_b (clk_b),`	`.inclock_b (clk_b),`
`.data_a (di_a),`	`.data_a (di_a),`
`.data_b (di_b),`	`.data_b (di_b),`
`.q_a (do_a),`	`.q_a (do_a),`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 10 and 142