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| Rev 39 |
Rev 46 |
| Line 90... |
Line 90... |
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#define DC_WISHBONE 0
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#define DC_WISHBONE 0
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#define DC_CPU0 1
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#define DC_CPU0 1
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#define DC_CPU1 2
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#define DC_CPU1 2
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// Defining access types for wishbone
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#define DBG_WB_WRITE8 0
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#define DBG_WB_WRITE16 1
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#define DBG_WB_WRITE32 2
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#define DBG_WB_READ8 4
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#define DBG_WB_READ16 5
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#define DBG_WB_READ32 6
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// Defining access types for wishbone
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#define DBG_CPU_WRITE 2
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#define DBG_CPU_READ 6
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// Manually figure the 5-bit reversed values again if they change
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// Manually figure the 5-bit reversed values again if they change
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#define DI_GO 0
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#define DI_GO 0
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#define DI_READ_CMD 1
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#define DI_READ_CMD 1
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#define DI_WRITE_CMD 2
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#define DI_WRITE_CMD 2
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#define DI_READ_CTRL 3
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#define DI_READ_CTRL 3
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| Line 116... |
Line 128... |
int dbg_reset();
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int dbg_reset();
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/* set instruction register of JTAG TAP */
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/* set instruction register of JTAG TAP */
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int dbg_set_tap_ir(uint32_t ir);
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int dbg_set_tap_ir(uint32_t ir);
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/* Set "scan chain" of debug unit (NOT JTAG TAP!) */
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/* Set "scan chain" of debug unit (NOT JTAG TAP!) */
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int dbg_set_chain(uint32_t chain);
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int dbg_set_chain(uint32_t chain);
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/* read a byte from wishbone */
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int dbg_wb_write8(uint32_t adr, uint8_t data);
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/* read a word from wishbone */
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/* read a word from wishbone */
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int dbg_wb_read32(uint32_t adr, uint32_t *data);
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int dbg_wb_read32(uint32_t adr, uint32_t *data);
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/* write a word to wishbone */
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/* write a word to wishbone */
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int dbg_wb_write32(uint32_t adr, uint32_t data);
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int dbg_wb_write32(uint32_t adr, uint32_t data);
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/* read a block from wishbone */
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/* read a block from wishbone */
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