URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or_debug_proxy/] [includes/] [or_debug_proxy.h] - Diff between revs 46 and 47

Rev 46	Rev 47
Line 139...	Line 139...
`/* read a block from wishbone */`	`/* read a block from wishbone */`
`int dbg_wb_read_block32(uint32_t adr, uint32_t *data, uint32_t len);`	`int dbg_wb_read_block32(uint32_t adr, uint32_t *data, uint32_t len);`
`/* write a block to wishbone */`	`/* write a block to wishbone */`
`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);`	`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);`
`/* read a register from cpu */`	`/* read a register from cpu */`
`int dbg_cpu0_read(uint32_t adr, uint32_t *data);`	`int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);`
`/* read a register from cpu module */`	`/* read a register from cpu module */`
`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);`	`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);`
`/* write a cpu register */`	`/* write a cpu register */`
`int dbg_cpu0_write(uint32_t adr, uint32_t data);`	`int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);`
`/* write a cpu module register */`	`/* write a cpu module register */`
`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);`	`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);`

`void print_usage(); // Self explanatory`	`void print_usage(); // Self explanatory`