OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or_debug_proxy/] [src/] [usb_functions.c] - Diff between revs 94 and 529

Show entire file | Details | Blame | View Log

Rev 94 Rev 529
Line 163... Line 163...
 
 
void usb_dbg_test() {
void usb_dbg_test() {
 
 
  uint32_t npc, ppc, r1;
  uint32_t npc, ppc, r1;
  unsigned char stalled;
  unsigned char stalled;
 
  uint32_t zero = 0;
 
 
  printf("Stalling or1k\n");
  printf("Stalling OR1K CPU0\n");
  err = dbg_cpu0_write_ctrl(0, 0x01);      // stall or1k
  err = dbg_cpu0_write_ctrl(0, 0x01);      // stall or1k
 
 
  err = dbg_cpu0_read_ctrl(0, &stalled);
  err = dbg_cpu0_read_ctrl(0, &stalled);
  if (!(stalled & 0x1)) {
  if (!(stalled & 0x1)) {
    printf("or1k should be stalled\n");   // check stall or1k
    printf("OR1K CPU0 should be stalled\n");   // check stall or1k
    exit(1);
    exit(1);
  }
  }
  uint32_t zero = 0;
 
 
  if (err)
 
    {
 
      printf("Error %d occured when attempting to stall CPU\n", err);
 
      goto do_exit;
 
    }
 
 
  /* Clear Debug Reason Register (DRR) 0x3015 */
  /* Clear Debug Reason Register (DRR) 0x3015 */
 
  if (!err)
  err = dbg_cpu0_write((6 << 11) + 21, &zero, 4);
  err = dbg_cpu0_write((6 << 11) + 21, &zero, 4);
 
  if (err)
 
  {
 
          printf("Error %d occured when writing CPU DRR register\n",err);
 
          goto do_exit;
 
 
 
  }
 
  if (!err)
  err = dbg_cpu0_read((0 << 11) + 16, &npc, 4);  /* Read NPC */
  err = dbg_cpu0_read((0 << 11) + 16, &npc, 4);  /* Read NPC */
 
  if (err)
 
  {
 
          printf("Error %d occured when reading CPU NPC\n",err);
 
          goto do_exit;
 
 
 
  }
 
  if (!err)
  err = dbg_cpu0_read((0 << 11) + 18, &ppc, 4);  /* Read PPC */
  err = dbg_cpu0_read((0 << 11) + 18, &ppc, 4);  /* Read PPC */
  err = dbg_cpu0_read(0x401, &r1, 4);  /* Read R1 */
  if (err)
 
  {
 
          printf("Error %d occured when reading CPU PPC\n",err);
 
          goto do_exit;
 
 
 
  }
 
  if (!err)
 
          err = dbg_cpu0_read(0x401, &r1, 4);  /* Read R1 */
  if (err)
  if (err)
    {
    {
      printf("Jtag error %d occured; exiting.", err);
          printf("Error %d occured when reading CPU GPR1\n",err);
      FT2232_USB_JTAG_CloseDevice();
          goto do_exit;
      exit(1);
 
    }
    }
 
 
  printf("Read      npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
  printf("Read      npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
 
 
  /*
  /*
  // Memory test - attempt to read and write massive arrays
  // Memory test - attempt to read and write massive arrays
  char biggest_array[65000];
  char biggest_array[65000];
Line 199... Line 228...
  printf("Writing array\n");
  printf("Writing array\n");
  err = usb_dbg_wb_write_block32(0, (uint32_t *)biggest_array, 65000);
  err = usb_dbg_wb_write_block32(0, (uint32_t *)biggest_array, 65000);
  printf("err = %d\n",err);
  printf("err = %d\n",err);
  */
  */
  return;
  return;
 
 
 
do_exit:
 
  printf("Exiting\n");
 
  FT2232_USB_JTAG_CloseDevice();
 
  exit(1);
}
}
 
 
 
 
 
 
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
Line 319... Line 353...
int usb_dbg_reset() {
int usb_dbg_reset() {
 
 
  // uint32_t err;
  // uint32_t err;
  uint32_t id;
  uint32_t id;
  uint32_t reinit_count=0;
  uint32_t reinit_count=0;
 
  int err;
 retry_jtag_init:
 retry_jtag_init:
  if (init_usb_jtag() > 0)
  err = init_usb_jtag();
 
  if (err)
 
  {
 
#ifdef DEBUG_USB_DRVR_FUNCS
 
          printf("init_usb_jtag error %d\n",err);
 
#endif
    return DBG_ERR_CRC;
    return DBG_ERR_CRC;
 
  }
 
 
  // Set ID code instruction in IR
  // Set ID code instruction in IR
  usb_set_tap_ir(JI_IDCODE);
  usb_set_tap_ir(JI_IDCODE);
 
 
  // Now read out the IDCODE for the device
  // Now read out the IDCODE for the device

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.