URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocAccess.cpp] - Diff between revs 44 and 49

Rev 44	Rev 49
Line 88...	Line 88...
`{`	`{`
`return or1200_except->ex_dslot;`	`return or1200_except->ex_dslot;`

`} // getExDslot ()`	`} // getExDslot ()`

	`//! Access for the id_pc register`

	`//! @return The value of the or1200_except.id_pc register`

	`uint32_t`
	`OrpsocAccess::getIdPC ()`
	`{`
	`return (or1200_except->get_id_pc) ();`

	`} // getIdPC ()`

`//! Access for the wb_pc register`	`//! Access for the wb_pc register`

`//! @return The value of the or1200_except.wb_insn register`	`//! @return The value of the or1200_except.wb_pc register`

`uint32_t`	`uint32_t`
`OrpsocAccess::getWbPC ()`	`OrpsocAccess::getWbPC ()`
`{`	`{`
`return (or1200_except->get_wb_pc) ();`	`return (or1200_except->get_wb_pc) ();`
Line 110...	Line 121...
`{`	`{`
`return (or1200_ctrl->get_wb_insn) ();`	`return (or1200_ctrl->get_wb_insn) ();`

`} // getWbInsn ()`	`} // getWbInsn ()`

	`//! Access for the id_insn register`

	`//! @return The value of the or1200_ctrl.wb_insn register`

	`uint32_t`
	`OrpsocAccess::getIdInsn ()`
	`{`
	`return (or1200_ctrl->get_id_insn) ();`

	`} // getIdInsn ()`

`//! Access for the OR1200 GPRs`	`//! Access for the OR1200 GPRs`

`//! These are extracted from memory using the Verilog function`	`//! These are extracted from memory using the Verilog function`