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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)

// 4'h2 set debug chain (dbg_set_command here) (input: chain value)

// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))

// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))

// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))

// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))

// 4'h5 cpu wr reg (inputs: address, data)

// 4'h5 cpu wr reg (inputs: address, data)

// 4'h6 cpu rd reg (input: address; output: data)

// 4'h6 cpu rd reg (input: address; output: data)

// 4'h8 wb rd 32 (input: address; output: data)

// 4'h8 wb rd 32 (input: address; output: data)

// 4'h9 wb wr block 32 (inputs: address, length, data)

// 4'h9 wb wr block 32 (inputs: address, length, data)

// 4'ha wb rd block 32 (inputs: address, length; output: data)

// 4'ha wb rd block 32 (inputs: address, length; output: data)

// 4'hb reset

// 4'hb reset

// 4'hc read jtag id (output: data)

// 4'hc read jtag id (output: data)

#define CMD_SET_DEBUG_CHAIN 0x2

#define CMD_SET_DEBUG_CHAIN 0x2

#define CMD_CPU_CTRL_WR 0x3

#define CMD_CPU_CTRL_WR 0x3

#define CMD_CPU_CTRL_RD 0x4

#define CMD_CPU_CTRL_RD 0x4

#define CMD_CPU_WR_REG 0x5

#define CMD_CPU_WR_REG 0x5

#define CMD_CPU_RD_REG 0x6

#define CMD_CPU_RD_REG 0x6

#define CMD_WB_RD32 0x8

#define CMD_WB_RD32 0x8

#define CMD_WB_BLOCK_WR32 0x9

#define CMD_WB_BLOCK_WR32 0x9

#define CMD_WB_BLOCK_RD32 0xa

#define CMD_WB_BLOCK_RD32 0xa

#define CMD_RESET 0xb

#define CMD_RESET 0xb

#define CMD_READ_JTAG_ID 0xc

#define CMD_READ_JTAG_ID 0xc