//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ////
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/// ////
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/// ORPSoC testbench ////
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/// ORPSoC testbench ////
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/// ////
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/// ////
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/// Instantiate ORPSoC, monitors, provide stimulus ////
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/// Instantiate ORPSoC, monitors, provide stimulus ////
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/// ////
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/// ////
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/// Julius Baxter, julius@opencores.org ////
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/// Julius Baxter, julius@opencores.org ////
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/// ////
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/// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "orpsoc-defines.v"
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`include "orpsoc-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "test-defines.v"
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`include "test-defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module orpsoc_testbench;
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module orpsoc_testbench;
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// Clock and reset signal registers
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// Clock and reset signal registers
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reg clk = 0;
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reg clk = 0;
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reg rst_n = 1; // Active LOW
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reg rst_n = 1; // Active LOW
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reg eth_clk = 0;
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reg eth_clk = 0;
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always
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always
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#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
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#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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always
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always
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#((`ETHERNET_CLOCK_PERIOD)/2) eth_clk <= ~eth_clk;
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#((`ETHERNET_CLOCK_PERIOD)/2) eth_clk <= ~eth_clk;
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`endif
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`endif
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// Reset, ACTIVE LOW
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// Reset, ACTIVE LOW
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initial
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initial
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begin
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begin
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#1;
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#1;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 1;
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rst_n <= 1;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 0;
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rst_n <= 0;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 1;
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rst_n <= 1;
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end
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end
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// Include design parameters file
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// Include design parameters file
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`include "orpsoc-params.v"
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`include "orpsoc-params.v"
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// Pullup bus for I2C
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// Pullup bus for I2C
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tri1 i2c_scl, i2c_sda;
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tri1 i2c_scl, i2c_sda;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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wire tdo_pad_o;
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wire tdo_pad_o;
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wire tck_pad_i;
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wire tck_pad_i;
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wire tms_pad_i;
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wire tms_pad_i;
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wire tdi_pad_i;
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wire tdi_pad_i;
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`endif
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`endif
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`ifdef UART0
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`ifdef UART0
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wire uart0_stx_pad_o;
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wire uart0_stx_pad_o;
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wire uart0_srx_pad_i;
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wire uart0_srx_pad_i;
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`endif
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`endif
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`ifdef GPIO0
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`ifdef GPIO0
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wire [gpio0_io_width-1:0] gpio0_io;
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wire [gpio0_io_width-1:0] gpio0_io;
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`endif
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`endif
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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wire [12:0] sdram_a_pad_o;
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wire [12:0] sdram_a_pad_o;
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wire [1:0] sdram_ba_pad_o;
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wire [1:0] sdram_ba_pad_o;
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wire sdram_cas_pad_o;
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wire sdram_cas_pad_o;
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wire sdram_cke_pad_o;
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wire sdram_cke_pad_o;
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wire sdram_cs_n_pad_o;
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wire sdram_cs_n_pad_o;
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wire [15:0] sdram_dq_pad_io;
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wire [15:0] sdram_dq_pad_io;
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wire [1:0] sdram_dqm_pad_o;
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wire [1:0] sdram_dqm_pad_o;
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wire sdram_ras_pad_o;
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wire sdram_ras_pad_o;
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wire sdram_we_pad_o;
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wire sdram_we_pad_o;
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`endif
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`endif
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`ifdef SPI0
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`ifdef SPI0
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wire spi0_mosi_o;
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wire spi0_mosi_o;
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wire spi0_miso_i;
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wire spi0_miso_i;
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wire spi0_sck_o;
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wire spi0_sck_o;
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wire spi0_hold_n_o;
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wire spi0_hold_n_o;
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wire spi0_w_n_o;
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wire spi0_w_n_o;
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wire [spi0_ss_width-1:0] spi0_ss_o;
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wire [spi0_ss_width-1:0] spi0_ss_o;
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`endif
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`endif
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`ifdef SPI1
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`ifdef SPI1
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wire spi1_mosi_o;
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wire spi1_mosi_o;
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wire spi1_miso_i;
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wire spi1_miso_i;
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wire spi1_sck_o;
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wire spi1_sck_o;
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wire [spi1_ss_width-1:0] spi1_ss_o;
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wire [spi1_ss_width-1:0] spi1_ss_o;
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`endif
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`endif
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`ifdef SPI2
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`ifdef SPI2
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wire spi2_mosi_o;
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wire spi2_mosi_o;
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wire spi2_miso_i;
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wire spi2_miso_i;
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wire spi2_sck_o;
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wire spi2_sck_o;
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wire [spi2_ss_width-1:0] spi2_ss_o;
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wire [spi2_ss_width-1:0] spi2_ss_o;
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`endif
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`endif
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`ifdef USB0
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`ifdef USB0
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wire usb0fullspeed_pad_o;
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wire usb0fullspeed_pad_o;
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wire usb0ctrl_pad_o;
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wire usb0ctrl_pad_o;
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wire [1:0] usb0dat_pad_o;
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wire [1:0] usb0dat_pad_o;
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wire [1:0] usb0dat_pad_i;
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wire [1:0] usb0dat_pad_i;
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`endif
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`endif
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`ifdef USB1
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`ifdef USB1
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wire usb1fullspeed_pad_o;
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wire usb1fullspeed_pad_o;
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wire usb1ctrl_pad_o;
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wire usb1ctrl_pad_o;
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wire [1:0] usb1dat_pad_o;
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wire [1:0] usb1dat_pad_o;
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wire [1:0] usb1dat_pad_i;
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wire [1:0] usb1dat_pad_i;
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`endif
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`endif
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`ifdef ETH0
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`ifdef ETH0
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`ifdef SMII0
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`ifdef SMII0
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parameter Td_smii = 2;
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parameter Td_smii = 2;
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wire #Td_smii eth0_smii_sync_pad_o;
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wire #Td_smii eth0_smii_sync_pad_o;
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wire #Td_smii eth0_smii_tx_pad_o;
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wire #Td_smii eth0_smii_tx_pad_o;
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wire #Td_smii eth0_smii_rx_pad_i;
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wire #Td_smii eth0_smii_rx_pad_i;
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`endif
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`endif
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wire mtx_clk_o;
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wire mtx_clk_o;
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wire [3:0] ethphy_mii_tx_d;
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wire [3:0] ethphy_mii_tx_d;
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wire ethphy_mii_tx_en;
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wire ethphy_mii_tx_en;
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wire ethphy_mii_tx_err;
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wire ethphy_mii_tx_err;
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wire mrx_clk_o;
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wire mrx_clk_o;
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wire [3:0] mrxd_o;
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wire [3:0] mrxd_o;
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wire mrxdv_o;
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wire mrxdv_o;
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wire mrxerr_o;
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wire mrxerr_o;
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wire mcoll_o;
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wire mcoll_o;
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wire mcrs_o;
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wire mcrs_o;
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wire ethphy_rst_n;
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wire ethphy_rst_n;
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wire eth0_mdc_pad_o;
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wire eth0_mdc_pad_o;
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wire eth0_md_pad_io;
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wire eth0_md_pad_io;
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`endif
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`endif
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orpsoc_top dut
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orpsoc_top dut
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(
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(
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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.tms_pad_i (tms_pad_i),
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.tms_pad_i (tms_pad_i),
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.tck_pad_i (tck_pad_i),
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.tck_pad_i (tck_pad_i),
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.tdi_pad_i (tdi_pad_i),
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.tdi_pad_i (tdi_pad_i),
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.tdo_pad_o (tdo_pad_o),
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.tdo_pad_o (tdo_pad_o),
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`endif
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`endif
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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.sdram_dq_pad_io (sdram_dq_pad_io),
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.sdram_dq_pad_io (sdram_dq_pad_io),
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.sdram_ba_pad_o (sdram_ba_pad_o),
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.sdram_ba_pad_o (sdram_ba_pad_o),
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.sdram_a_pad_o (sdram_a_pad_o),
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.sdram_a_pad_o (sdram_a_pad_o),
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.sdram_cs_n_pad_o (sdram_cs_n_pad_o),
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.sdram_cs_n_pad_o (sdram_cs_n_pad_o),
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.sdram_ras_pad_o (sdram_ras_pad_o),
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.sdram_ras_pad_o (sdram_ras_pad_o),
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.sdram_cas_pad_o (sdram_cas_pad_o),
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.sdram_cas_pad_o (sdram_cas_pad_o),
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.sdram_we_pad_o (sdram_we_pad_o),
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.sdram_we_pad_o (sdram_we_pad_o),
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.sdram_dqm_pad_o (sdram_dqm_pad_o),
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.sdram_dqm_pad_o (sdram_dqm_pad_o),
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.sdram_cke_pad_o (sdram_cke_pad_o),
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.sdram_cke_pad_o (sdram_cke_pad_o),
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`endif
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`endif
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`ifdef UART0
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`ifdef UART0
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.uart0_stx_pad_o (uart0_stx_pad_o),
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.uart0_stx_pad_o (uart0_stx_pad_o),
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.uart0_srx_pad_i (uart0_srx_pad_i),
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.uart0_srx_pad_i (uart0_srx_pad_i),
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`endif
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`endif
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`ifdef SPI0
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`ifdef SPI0
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.spi0_sck_o (spi0_sck_o),
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.spi0_sck_o (spi0_sck_o),
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.spi0_mosi_o (spi0_mosi_o),
|
.spi0_mosi_o (spi0_mosi_o),
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.spi0_miso_i (spi0_miso_i),
|
.spi0_miso_i (spi0_miso_i),
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`ifdef SPI0_SLAVE_SELECTS
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`ifdef SPI0_SLAVE_SELECTS
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.spi0_ss_o (spi0_ss_o),
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.spi0_ss_o (spi0_ss_o),
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`endif
|
`endif
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.spi0_hold_n_o (spi0_hold_n_o),
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.spi0_hold_n_o (spi0_hold_n_o),
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.spi0_w_n_o (spi0_w_n_o),
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.spi0_w_n_o (spi0_w_n_o),
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`endif
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`endif
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`ifdef SPI1
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`ifdef SPI1
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.spi1_sck_o (spi1_sck_o),
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.spi1_sck_o (spi1_sck_o),
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.spi1_mosi_o (spi1_mosi_o),
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.spi1_mosi_o (spi1_mosi_o),
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.spi1_miso_i (spi1_miso_i),
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.spi1_miso_i (spi1_miso_i),
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`ifdef SPI1_SLAVE_SELECTS
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`ifdef SPI1_SLAVE_SELECTS
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.spi1_ss_o (spi1_ss_o),
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.spi1_ss_o (spi1_ss_o),
|
`endif
|
`endif
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`endif
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`endif
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`ifdef SPI2
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`ifdef SPI2
|
.spi2_sck_o (spi2_sck_o),
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.spi2_sck_o (spi2_sck_o),
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.spi2_mosi_o (spi2_mosi_o),
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.spi2_mosi_o (spi2_mosi_o),
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.spi2_miso_i (spi2_miso_i),
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.spi2_miso_i (spi2_miso_i),
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`ifdef SPI2_SLAVE_SELECTS
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`ifdef SPI2_SLAVE_SELECTS
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.spi2_ss_o (spi2_ss_o),
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.spi2_ss_o (spi2_ss_o),
|
`endif
|
`endif
|
`endif
|
`endif
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`ifdef USB0
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`ifdef USB0
|
.usb0dat_pad_o (usb0dat_pad_o),
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.usb0dat_pad_o (usb0dat_pad_o),
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.usb0ctrl_pad_o (usb0ctrl_pad_o),
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.usb0ctrl_pad_o (usb0ctrl_pad_o),
|
.usb0fullspeed_pad_o (usb0fullspeed_pad_o),
|
.usb0fullspeed_pad_o (usb0fullspeed_pad_o),
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.usb0dat_pad_i (usb0dat_pad_i),
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.usb0dat_pad_i (usb0dat_pad_i),
|
`endif
|
`endif
|
`ifdef USB1
|
`ifdef USB1
|
.usb1dat_pad_o (usb1dat_pad_o),
|
.usb1dat_pad_o (usb1dat_pad_o),
|
.usb1ctrl_pad_o (usb1ctrl_pad_o),
|
.usb1ctrl_pad_o (usb1ctrl_pad_o),
|
.usb1fullspeed_pad_o (usb1fullspeed_pad_o),
|
.usb1fullspeed_pad_o (usb1fullspeed_pad_o),
|
.usb1dat_pad_i (usb1dat_pad_i),
|
.usb1dat_pad_i (usb1dat_pad_i),
|
`endif
|
`endif
|
`ifdef I2C0
|
`ifdef I2C0
|
.i2c0_sda_io (i2c_sda),
|
.i2c0_sda_io (i2c_sda),
|
.i2c0_scl_io (i2c_scl),
|
.i2c0_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef I2C1
|
`ifdef I2C1
|
.i2c1_sda_io (i2c_sda),
|
.i2c1_sda_io (i2c_sda),
|
.i2c1_scl_io (i2c_scl),
|
.i2c1_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef I2C2
|
`ifdef I2C2
|
.i2c2_sda_io (i2c_sda),
|
.i2c2_sda_io (i2c_sda),
|
.i2c2_scl_io (i2c_scl),
|
.i2c2_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef I2C3
|
`ifdef I2C3
|
.i2c3_sda_io (i2c_sda),
|
.i2c3_sda_io (i2c_sda),
|
.i2c3_scl_io (i2c_scl),
|
.i2c3_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef GPIO0
|
`ifdef GPIO0
|
.gpio0_io (gpio0_io),
|
.gpio0_io (gpio0_io),
|
`endif
|
`endif
|
`ifdef ETH0
|
`ifdef ETH0
|
`ifdef SMII0
|
`ifdef SMII0
|
.eth0_smii_sync_pad_o (eth0_smii_sync_pad_o),
|
.eth0_smii_sync_pad_o (eth0_smii_sync_pad_o),
|
.eth0_smii_tx_pad_o (eth0_smii_tx_pad_o),
|
.eth0_smii_tx_pad_o (eth0_smii_tx_pad_o),
|
.eth0_smii_rx_pad_i (eth0_smii_rx_pad_i),
|
.eth0_smii_rx_pad_i (eth0_smii_rx_pad_i),
|
`else
|
`else
|
.eth0_tx_clk (mtx_clk_o),
|
.eth0_tx_clk (mtx_clk_o),
|
.eth0_tx_data (ethphy_mii_tx_d),
|
.eth0_tx_data (ethphy_mii_tx_d),
|
.eth0_tx_en (ethphy_mii_tx_en),
|
.eth0_tx_en (ethphy_mii_tx_en),
|
.eth0_tx_er (ethphy_mii_tx_err),
|
.eth0_tx_er (ethphy_mii_tx_err),
|
.eth0_rx_clk (mrx_clk_o),
|
.eth0_rx_clk (mrx_clk_o),
|
.eth0_rx_data (mrxd_o),
|
.eth0_rx_data (mrxd_o),
|
.eth0_dv (mrxdv_o),
|
.eth0_dv (mrxdv_o),
|
.eth0_rx_er (mrxerr_o),
|
.eth0_rx_er (mrxerr_o),
|
.eth0_col (mcoll_o),
|
.eth0_col (mcoll_o),
|
.eth0_crs (mcrs_o),
|
.eth0_crs (mcrs_o),
|
`endif // !`ifdef SMII0
|
`endif // !`ifdef SMII0
|
`ifdef ETH0_PHY_RST
|
`ifdef ETH0_PHY_RST
|
.eth0_rst_n_o (ethphy_rst_n),
|
.eth0_rst_n_o (ethphy_rst_n),
|
`endif
|
`endif
|
.eth0_mdc_pad_o (eth0_mdc_pad_o),
|
.eth0_mdc_pad_o (eth0_mdc_pad_o),
|
.eth0_md_pad_io (eth0_md_pad_io),
|
.eth0_md_pad_io (eth0_md_pad_io),
|
`endif // `ifdef ETH0
|
`endif // `ifdef ETH0
|
`ifdef ETH_CLK
|
`ifdef ETH_CLK
|
.eth_clk_pad_i (eth_clk),
|
.eth_clk_pad_i (eth_clk),
|
`endif
|
`endif
|
|
`ifdef SDC_CONTROLLER
|
|
.sdc_cmd_pad_io (),
|
|
.sdc_dat_pad_io (),
|
|
.sdc_clk_pad_o (),
|
|
.sdc_card_detect_pad_i (1'b0),
|
|
`endif
|
|
|
.sys_clk_pad_i (clk),
|
.sys_clk_pad_i (clk),
|
.rst_n_pad_i (rst_n)
|
.rst_n_pad_i (rst_n)
|
);
|
);
|
|
|
//
|
//
|
// Instantiate OR1200 monitor
|
// Instantiate OR1200 monitor
|
//
|
//
|
or1200_monitor monitor();
|
or1200_monitor monitor();
|
|
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
`define CPU_ic_top or1200_ic_top
|
`define CPU_ic_top or1200_ic_top
|
`define CPU_dc_top or1200_dc_top
|
`define CPU_dc_top or1200_dc_top
|
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
|
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
|
always @(posedge ic_en)
|
always @(posedge ic_en)
|
$display("Or1200 IC enabled at %t", $time);
|
$display("Or1200 IC enabled at %t", $time);
|
|
|
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
|
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
|
always @(posedge dc_en)
|
always @(posedge dc_en)
|
$display("Or1200 DC enabled at %t", $time);
|
$display("Or1200 DC enabled at %t", $time);
|
`endif
|
`endif
|
|
|
|
|
`ifdef JTAG_DEBUG
|
`ifdef JTAG_DEBUG
|
`ifdef VPI_DEBUG
|
`ifdef VPI_DEBUG
|
// Debugging interface
|
// Debugging interface
|
vpi_debug_module vpi_dbg
|
vpi_debug_module vpi_dbg
|
(
|
(
|
.tms(tms_pad_i),
|
.tms(tms_pad_i),
|
.tck(tck_pad_i),
|
.tck(tck_pad_i),
|
.tdi(tdi_pad_i),
|
.tdi(tdi_pad_i),
|
.tdo(tdo_pad_o)
|
.tdo(tdo_pad_o)
|
);
|
);
|
`else
|
`else
|
// If no VPI debugging, tie off JTAG inputs
|
// If no VPI debugging, tie off JTAG inputs
|
assign tdi_pad_i = 1;
|
assign tdi_pad_i = 1;
|
assign tck_pad_i = 0;
|
assign tck_pad_i = 0;
|
assign tms_pad_i = 1;
|
assign tms_pad_i = 1;
|
`endif // !`ifdef VPI_DEBUG_ENABLE
|
`endif // !`ifdef VPI_DEBUG_ENABLE
|
`endif // `ifdef JTAG_DEBUG
|
`endif // `ifdef JTAG_DEBUG
|
|
|
`ifdef SPI0
|
`ifdef SPI0
|
// SPI Flash
|
// SPI Flash
|
AT26DFxxx spi0_flash
|
AT26DFxxx spi0_flash
|
(// Outputs
|
(// Outputs
|
.SO (spi0_miso_i),
|
.SO (spi0_miso_i),
|
// Inputs
|
// Inputs
|
.CSB (spi0_ss_o),
|
.CSB (spi0_ss_o),
|
.SCK (spi0_sck_o),
|
.SCK (spi0_sck_o),
|
.SI (spi0_mosi_o),
|
.SI (spi0_mosi_o),
|
.WPB (spi0_w_n_o)
|
.WPB (spi0_w_n_o)
|
);
|
);
|
`endif // `ifdef SPI0
|
`endif // `ifdef SPI0
|
|
|
`ifdef ETH0
|
`ifdef ETH0
|
// ORDB1 with OREEB1 always uses SMII, but keep this anyway.
|
// ORDB1 with OREEB1 always uses SMII, but keep this anyway.
|
`ifdef SMII0
|
`ifdef SMII0
|
|
|
wire fast_ethernet, duplex, link;
|
wire fast_ethernet, duplex, link;
|
wire eth_clk_smii_phy;
|
wire eth_clk_smii_phy;
|
|
|
assign eth_clk_smii_phy = eth_clk;
|
assign eth_clk_smii_phy = eth_clk;
|
|
|
/* Converts SMII back to MII */
|
/* Converts SMII back to MII */
|
smii_phy smii_phyend
|
smii_phy smii_phyend
|
(
|
(
|
// Outputs
|
// Outputs
|
.smii_rx (/*eth0_smii_rx_pad_i*/), /* SMII RX */
|
.smii_rx (/*eth0_smii_rx_pad_i*/), /* SMII RX */
|
.ethphy_mii_tx_d (ethphy_mii_tx_d[3:0]), /* MII TX */
|
.ethphy_mii_tx_d (ethphy_mii_tx_d[3:0]), /* MII TX */
|
.ethphy_mii_tx_en (ethphy_mii_tx_en), /* MII TX */
|
.ethphy_mii_tx_en (ethphy_mii_tx_en), /* MII TX */
|
.ethphy_mii_tx_err (ethphy_mii_tx_err), /* MII TX */
|
.ethphy_mii_tx_err (ethphy_mii_tx_err), /* MII TX */
|
// Inputs
|
// Inputs
|
.smii_tx (eth0_smii_tx_pad_o), /* SMII TX */
|
.smii_tx (eth0_smii_tx_pad_o), /* SMII TX */
|
.smii_sync (eth0_smii_sync_pad_o), /* SMII SYNC */
|
.smii_sync (eth0_smii_sync_pad_o), /* SMII SYNC */
|
.ethphy_mii_tx_clk (mtx_clk_o), /* MII TX */
|
.ethphy_mii_tx_clk (mtx_clk_o), /* MII TX */
|
|
|
.ethphy_mii_rx_d (mrxd_o[3:0]), /* MII RX */
|
.ethphy_mii_rx_d (mrxd_o[3:0]), /* MII RX */
|
.ethphy_mii_rx_dv (mrxdv_o), /* MII RX */
|
.ethphy_mii_rx_dv (mrxdv_o), /* MII RX */
|
.ethphy_mii_rx_err (mrxerr_o), /* MII RX */
|
.ethphy_mii_rx_err (mrxerr_o), /* MII RX */
|
.ethphy_mii_rx_clk (mrx_clk_o), /* MII RX */
|
.ethphy_mii_rx_clk (mrx_clk_o), /* MII RX */
|
|
|
.ethphy_mii_mcoll (),
|
.ethphy_mii_mcoll (),
|
.ethphy_mii_crs (mcrs_o),
|
.ethphy_mii_crs (mcrs_o),
|
.fast_ethernet (fast_ethernet),
|
.fast_ethernet (fast_ethernet),
|
.duplex (duplex),
|
.duplex (duplex),
|
.link (link),
|
.link (link),
|
.clk (eth_clk_smii_phy),
|
.clk (eth_clk_smii_phy),
|
.rst_n (rst_n));
|
.rst_n (rst_n));
|
|
|
`endif // `ifdef SMII0
|
`endif // `ifdef SMII0
|
|
|
/* TX/RXes packets and checks them, enabled when ethernet MAC is */
|
/* TX/RXes packets and checks them, enabled when ethernet MAC is */
|
`include "eth_stim.v"
|
`include "eth_stim.v"
|
|
|
eth_phy eth_phy0
|
eth_phy eth_phy0
|
(
|
(
|
// Outputs
|
// Outputs
|
.mtx_clk_o (mtx_clk_o),
|
.mtx_clk_o (mtx_clk_o),
|
.mrx_clk_o (mrx_clk_o),
|
.mrx_clk_o (mrx_clk_o),
|
.mrxd_o (mrxd_o[3:0]),
|
.mrxd_o (mrxd_o[3:0]),
|
.mrxdv_o (mrxdv_o),
|
.mrxdv_o (mrxdv_o),
|
.mrxerr_o (mrxerr_o),
|
.mrxerr_o (mrxerr_o),
|
.mcoll_o (mcoll_o),
|
.mcoll_o (mcoll_o),
|
.mcrs_o (mcrs_o),
|
.mcrs_o (mcrs_o),
|
// Sideband outputs for smii converter --jb
|
// Sideband outputs for smii converter --jb
|
.link_o (link),
|
.link_o (link),
|
.speed_o (fast_ethernet),
|
.speed_o (fast_ethernet),
|
.duplex_o (duplex),
|
.duplex_o (duplex),
|
.smii_clk_i (eth_clk),
|
.smii_clk_i (eth_clk),
|
.smii_sync_i (eth0_smii_sync_pad_o),
|
.smii_sync_i (eth0_smii_sync_pad_o),
|
.smii_rx_o (eth0_smii_rx_pad_i),
|
.smii_rx_o (eth0_smii_rx_pad_i),
|
// Inouts
|
// Inouts
|
.md_io (eth0_md_pad_io),
|
.md_io (eth0_md_pad_io),
|
// Inputs
|
// Inputs
|
`ifndef ETH0_PHY_RST
|
`ifndef ETH0_PHY_RST
|
// If no reset out from the design, hook up to the board's active low rst
|
// If no reset out from the design, hook up to the board's active low rst
|
.m_rst_n_i (rst_n),
|
.m_rst_n_i (rst_n),
|
`else
|
`else
|
.m_rst_n_i (ethphy_rst_n),
|
.m_rst_n_i (ethphy_rst_n),
|
`endif
|
`endif
|
.mtxd_i (ethphy_mii_tx_d[3:0]),
|
.mtxd_i (ethphy_mii_tx_d[3:0]),
|
.mtxen_i (ethphy_mii_tx_en),
|
.mtxen_i (ethphy_mii_tx_en),
|
.mtxerr_i (ethphy_mii_tx_err),
|
.mtxerr_i (ethphy_mii_tx_err),
|
.mdc_i (eth0_mdc_pad_o));
|
.mdc_i (eth0_mdc_pad_o));
|
|
|
`endif // `ifdef ETH0
|
`endif // `ifdef ETH0
|
|
|
// Simple slaves to test the SPI masters
|
// Simple slaves to test the SPI masters
|
`ifdef SPI1
|
`ifdef SPI1
|
`ifdef SPI1_SLAVE_SELECTS
|
`ifdef SPI1_SLAVE_SELECTS
|
wire [spi1_ss_width-1:0] spi1_leds;
|
wire [spi1_ss_width-1:0] spi1_leds;
|
genvar spi1;
|
genvar spi1;
|
generate
|
generate
|
for (spi1 = 0; spi1 < spi1_ss_width; spi1 = spi1+1) begin : spi1_gen
|
for (spi1 = 0; spi1 < spi1_ss_width; spi1 = spi1+1) begin : spi1_gen
|
spi_slave spi1_slave
|
spi_slave spi1_slave
|
(.clk(clk),
|
(.clk(clk),
|
.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
|
.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
|
.MISO(spi1_miso_i), .SSEL(spi1_ss_o[spi1]),
|
.MISO(spi1_miso_i), .SSEL(spi1_ss_o[spi1]),
|
.LED(spi1_leds[spi1]));
|
.LED(spi1_leds[spi1]));
|
end
|
end
|
endgenerate
|
endgenerate
|
`else // !`ifdef SPI1_SLAVE_SELECTS
|
`else // !`ifdef SPI1_SLAVE_SELECTS
|
spi_slave spi1_slave
|
spi_slave spi1_slave
|
(.clk(clk),
|
(.clk(clk),
|
.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
|
.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
|
.MISO(spi1_miso_i), .SSEL(1'b0),
|
.MISO(spi1_miso_i), .SSEL(1'b0),
|
.LED());
|
.LED());
|
`endif // !`ifdef SPI1_SLAVE_SELECTS
|
`endif // !`ifdef SPI1_SLAVE_SELECTS
|
`endif
|
`endif
|
|
|
`ifdef SPI2
|
`ifdef SPI2
|
`ifdef SPI2_SLAVE_SELECTS
|
`ifdef SPI2_SLAVE_SELECTS
|
wire [spi2_ss_width-1:0] spi2_leds;
|
wire [spi2_ss_width-1:0] spi2_leds;
|
genvar spi2;
|
genvar spi2;
|
generate
|
generate
|
for (spi2 = 0; spi2 < spi2_ss_width; spi2 = spi2+1) begin : spi2_gen
|
for (spi2 = 0; spi2 < spi2_ss_width; spi2 = spi2+1) begin : spi2_gen
|
spi_slave spi2_slave
|
spi_slave spi2_slave
|
(.clk(clk),
|
(.clk(clk),
|
.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
|
.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
|
.MISO(spi2_miso_i), .SSEL(spi2_ss_o[spi2]),
|
.MISO(spi2_miso_i), .SSEL(spi2_ss_o[spi2]),
|
.LED(spi2_leds[spi2]));
|
.LED(spi2_leds[spi2]));
|
end
|
end
|
endgenerate
|
endgenerate
|
`else // !`ifdef SPI2_SLAVE_SELECTS
|
`else // !`ifdef SPI2_SLAVE_SELECTS
|
spi_slave spi2_slave
|
spi_slave spi2_slave
|
(.clk(clk),
|
(.clk(clk),
|
.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
|
.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
|
.MISO(spi2_miso_i), .SSEL(1'b0),
|
.MISO(spi2_miso_i), .SSEL(1'b0),
|
.LED());
|
.LED());
|
`endif // !`ifdef SPI2_SLAVE_SELECTS
|
`endif // !`ifdef SPI2_SLAVE_SELECTS
|
`endif
|
`endif
|
|
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
|
parameter TPROP_PCB = 2.0;
|
parameter TPROP_PCB = 2.0;
|
reg [12:0] sdram_a_pad_o_to_sdram;
|
reg [12:0] sdram_a_pad_o_to_sdram;
|
reg [1:0] sdram_ba_pad_o_to_sdram;
|
reg [1:0] sdram_ba_pad_o_to_sdram;
|
reg sdram_cas_pad_o_to_sdram;
|
reg sdram_cas_pad_o_to_sdram;
|
reg sdram_cke_pad_o_to_sdram;
|
reg sdram_cke_pad_o_to_sdram;
|
reg sdram_cs_n_pad_o_to_sdram;
|
reg sdram_cs_n_pad_o_to_sdram;
|
wire [15:0] sdram_dq_pad_io_to_sdram;
|
wire [15:0] sdram_dq_pad_io_to_sdram;
|
reg [1:0] sdram_dqm_pad_o_to_sdram;
|
reg [1:0] sdram_dqm_pad_o_to_sdram;
|
reg sdram_ras_pad_o_to_sdram;
|
reg sdram_ras_pad_o_to_sdram;
|
reg sdram_we_pad_o_to_sdram;
|
reg sdram_we_pad_o_to_sdram;
|
|
|
always @( * ) begin
|
always @( * ) begin
|
sdram_a_pad_o_to_sdram <= #(TPROP_PCB) sdram_a_pad_o;
|
sdram_a_pad_o_to_sdram <= #(TPROP_PCB) sdram_a_pad_o;
|
sdram_ba_pad_o_to_sdram <= #(TPROP_PCB) sdram_ba_pad_o;
|
sdram_ba_pad_o_to_sdram <= #(TPROP_PCB) sdram_ba_pad_o;
|
sdram_cas_pad_o_to_sdram <= #(TPROP_PCB) sdram_cas_pad_o;
|
sdram_cas_pad_o_to_sdram <= #(TPROP_PCB) sdram_cas_pad_o;
|
sdram_cke_pad_o_to_sdram <= #(TPROP_PCB) sdram_cke_pad_o;
|
sdram_cke_pad_o_to_sdram <= #(TPROP_PCB) sdram_cke_pad_o;
|
sdram_cs_n_pad_o_to_sdram <= #(TPROP_PCB) sdram_cs_n_pad_o;
|
sdram_cs_n_pad_o_to_sdram <= #(TPROP_PCB) sdram_cs_n_pad_o;
|
sdram_dqm_pad_o_to_sdram <= #(TPROP_PCB) sdram_dqm_pad_o;
|
sdram_dqm_pad_o_to_sdram <= #(TPROP_PCB) sdram_dqm_pad_o;
|
sdram_ras_pad_o_to_sdram <= #(TPROP_PCB) sdram_ras_pad_o;
|
sdram_ras_pad_o_to_sdram <= #(TPROP_PCB) sdram_ras_pad_o;
|
sdram_we_pad_o_to_sdram <= #(TPROP_PCB) sdram_we_pad_o;
|
sdram_we_pad_o_to_sdram <= #(TPROP_PCB) sdram_we_pad_o;
|
end
|
end
|
|
|
genvar dqwd;
|
genvar dqwd;
|
generate
|
generate
|
for (dqwd = 0;dqwd < 16 ;dqwd = dqwd+1) begin : dq_delay
|
for (dqwd = 0;dqwd < 16 ;dqwd = dqwd+1) begin : dq_delay
|
wiredelay #
|
wiredelay #
|
(
|
(
|
.Delay_g (TPROP_PCB),
|
.Delay_g (TPROP_PCB),
|
.Delay_rd (TPROP_PCB)
|
.Delay_rd (TPROP_PCB)
|
)
|
)
|
u_delay_dq
|
u_delay_dq
|
(
|
(
|
.A (sdram_dq_pad_io[dqwd]),
|
.A (sdram_dq_pad_io[dqwd]),
|
.B (sdram_dq_pad_io_to_sdram[dqwd]),
|
.B (sdram_dq_pad_io_to_sdram[dqwd]),
|
.reset (rst_n)
|
.reset (rst_n)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// SDRAM
|
// SDRAM
|
mt48lc16m16a2 sdram0
|
mt48lc16m16a2 sdram0
|
(
|
(
|
// Inouts
|
// Inouts
|
.Dq (sdram_dq_pad_io_to_sdram),
|
.Dq (sdram_dq_pad_io_to_sdram),
|
// Inputs
|
// Inputs
|
.Addr (sdram_a_pad_o_to_sdram),
|
.Addr (sdram_a_pad_o_to_sdram),
|
.Ba (sdram_ba_pad_o_to_sdram),
|
.Ba (sdram_ba_pad_o_to_sdram),
|
.Clk (clk),
|
.Clk (clk),
|
.Cke (sdram_cke_pad_o_to_sdram),
|
.Cke (sdram_cke_pad_o_to_sdram),
|
.Cs_n (sdram_cs_n_pad_o_to_sdram),
|
.Cs_n (sdram_cs_n_pad_o_to_sdram),
|
.Ras_n (sdram_ras_pad_o_to_sdram),
|
.Ras_n (sdram_ras_pad_o_to_sdram),
|
.Cas_n (sdram_cas_pad_o_to_sdram),
|
.Cas_n (sdram_cas_pad_o_to_sdram),
|
.We_n (sdram_we_pad_o_to_sdram),
|
.We_n (sdram_we_pad_o_to_sdram),
|
.Dqm (sdram_dqm_pad_o_to_sdram));
|
.Dqm (sdram_dqm_pad_o_to_sdram));
|
`endif // `ifdef VERSATILE_SDRAM
|
`endif // `ifdef VERSATILE_SDRAM
|
|
|
`ifdef VCD
|
`ifdef VCD
|
reg vcd_go = 0;
|
reg vcd_go = 0;
|
always @(vcd_go)
|
always @(vcd_go)
|
begin
|
begin
|
|
|
`ifdef VCD_DELAY
|
`ifdef VCD_DELAY
|
#(`VCD_DELAY);
|
#(`VCD_DELAY);
|
`endif
|
`endif
|
|
|
// Delay by x insns
|
// Delay by x insns
|
`ifdef VCD_DELAY_INSNS
|
`ifdef VCD_DELAY_INSNS
|
#10; // Delay until after the value becomes valid
|
#10; // Delay until after the value becomes valid
|
while (monitor.insns < `VCD_DELAY_INSNS)
|
while (monitor.insns < `VCD_DELAY_INSNS)
|
@(posedge clk);
|
@(posedge clk);
|
`endif
|
`endif
|
|
|
`ifdef SIMULATOR_MODELSIM
|
`ifdef SIMULATOR_MODELSIM
|
// Modelsim can GZip VCDs on the fly if given in the suffix
|
// Modelsim can GZip VCDs on the fly if given in the suffix
|
`define VCD_SUFFIX ".vcd.gz"
|
`define VCD_SUFFIX ".vcd.gz"
|
`else
|
`else
|
`define VCD_SUFFIX ".vcd"
|
`define VCD_SUFFIX ".vcd"
|
`endif
|
`endif
|
|
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
`endif
|
`endif
|
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
`ifndef VCD_DEPTH
|
`ifndef VCD_DEPTH
|
`define VCD_DEPTH 0
|
`define VCD_DEPTH 0
|
`endif
|
`endif
|
$dumpvars(`VCD_DEPTH);
|
$dumpvars(`VCD_DEPTH);
|
|
|
end
|
end
|
`endif // `ifdef VCD
|
`endif // `ifdef VCD
|
|
|
initial
|
initial
|
begin
|
begin
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
|
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
|
`TEST_NAME_STRING );
|
`TEST_NAME_STRING );
|
`endif
|
`endif
|
|
|
`ifdef VCD
|
`ifdef VCD
|
vcd_go = 1;
|
vcd_go = 1;
|
`endif
|
`endif
|
|
|
end // initial begin
|
end // initial begin
|
|
|
`ifdef END_TIME
|
`ifdef END_TIME
|
initial begin
|
initial begin
|
#(`END_TIME);
|
#(`END_TIME);
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* Finish simulation due to END_TIME being set at %t", $time);
|
$display("* Finish simulation due to END_TIME being set at %t", $time);
|
`endif
|
`endif
|
$finish;
|
$finish;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef END_INSNS
|
`ifdef END_INSNS
|
initial begin
|
initial begin
|
#10
|
#10
|
while (monitor.insns < `END_INSNS)
|
while (monitor.insns < `END_INSNS)
|
@(posedge clk);
|
@(posedge clk);
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* Finish simulation due to END_INSNS count (%d) reached at %t",
|
$display("* Finish simulation due to END_INSNS count (%d) reached at %t",
|
`END_INSNS, $time);
|
`END_INSNS, $time);
|
`endif
|
`endif
|
$finish;
|
$finish;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef UART0
|
`ifdef UART0
|
//
|
//
|
// UART0 decoder
|
// UART0 decoder
|
//
|
//
|
uart_decoder
|
uart_decoder
|
#(
|
#(
|
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
|
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
|
)
|
)
|
uart0_decoder
|
uart0_decoder
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.uart_tx(uart0_stx_pad_o)
|
.uart_tx(uart0_stx_pad_o)
|
);
|
);
|
|
|
// Loopback UART lines
|
// Loopback UART lines
|
assign uart0_srx_pad_i = uart0_stx_pad_o;
|
assign uart0_srx_pad_i = uart0_stx_pad_o;
|
|
|
`endif // `ifdef UART0
|
`endif // `ifdef UART0
|
|
|
`ifdef USB0
|
`ifdef USB0
|
// USB testbench setup...
|
// USB testbench setup...
|
// All USB testbenches disabled for now
|
// All USB testbenches disabled for now
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
`include "wishBoneBus_h.v"
|
`include "wishBoneBus_h.v"
|
`include "usbHostSlave_h.v"
|
`include "usbHostSlave_h.v"
|
`include "usbSlaveControl_h.v"
|
`include "usbSlaveControl_h.v"
|
`include "usbHostSlave_h.v"
|
`include "usbHostSlave_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
// The actual file with stimulus:
|
// The actual file with stimulus:
|
`include "usb_hostslave_tb.v"
|
`include "usb_hostslave_tb.v"
|
|
|
`endif
|
`endif
|
|
|
endmodule // orpsoc_testbench
|
endmodule // orpsoc_testbench
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
|
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
|
// verilog-library-files:()
|
// verilog-library-files:()
|
// verilog-library-extensions:(".v" ".h")
|
// verilog-library-extensions:(".v" ".h")
|
// End:
|
// End:
|
|
|
|
|
