/*
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/*
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*
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*
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* Clock, reset generation unit
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* Clock, reset generation unit
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*
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*
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* Implements clock generation according to design defines
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* Implements clock generation according to design defines
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*
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*
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*/
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*/
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "orpsoc-defines.v"
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`include "orpsoc-defines.v"
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`include "synthesis-defines.v"
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`include "synthesis-defines.v"
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module clkgen
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module clkgen
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(
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(
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// Main clocks in, depending on board
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// Main clocks in, depending on board
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sys_clk_pad_i,
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sys_clk_pad_i,
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// Wishbone clock and reset out
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// Wishbone clock and reset out
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wb_clk_o,
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wb_clk_o,
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wb_rst_o,
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wb_rst_o,
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// JTAG clock
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// JTAG clock
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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tck_pad_i,
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tck_pad_i,
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dbg_tck_o,
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dbg_tck_o,
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`endif
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`endif
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// Main memory clocks
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// Main memory clocks
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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sdram_clk_o,
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sdram_clk_o,
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sdram_rst_o,
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sdram_rst_o,
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`endif
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`endif
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// Peripheral clocks
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// Peripheral clocks
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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eth_clk_pad_i,
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eth_clk_pad_i,
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eth_clk_o,
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eth_clk_o,
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eth_rst_o,
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eth_rst_o,
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`endif
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`endif
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`ifdef USB_CLK
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`ifdef USB_CLK
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usb_clk_o,
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usb_clk_o,
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`endif
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`endif
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// Asynchronous, active low reset in
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// Asynchronous, active low reset in
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rst_n_pad_i
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rst_n_pad_i
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);
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);
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input sys_clk_pad_i;
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input sys_clk_pad_i;
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output wb_rst_o;
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output wb_rst_o;
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output wb_clk_o;
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output wb_clk_o;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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input tck_pad_i;
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input tck_pad_i;
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output dbg_tck_o;
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output dbg_tck_o;
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`endif
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`endif
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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output sdram_clk_o;
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output sdram_clk_o;
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output sdram_rst_o;
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output sdram_rst_o;
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`endif
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`endif
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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input eth_clk_pad_i;
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input eth_clk_pad_i;
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output eth_clk_o;
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output eth_clk_o;
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output eth_rst_o;
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output eth_rst_o;
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`endif
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`endif
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`ifdef USB_CLK
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`ifdef USB_CLK
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output usb_clk_o;
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output usb_clk_o;
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`endif
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`endif
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// Asynchronous, active low reset (pushbutton, typically)
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// Asynchronous, active low reset (pushbutton, typically)
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input rst_n_pad_i;
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input rst_n_pad_i;
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// First, deal with the asychronous reset
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// First, deal with the asychronous reset
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wire async_rst;
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wire async_rst;
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wire async_rst_n;
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wire async_rst_n;
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reset_buffer reset_gbuf
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assign async_rst_n = rst_n_pad_i;
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(
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.GL(async_rst_n),
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.CLK(rst_n_pad_i)
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);
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// Everyone likes active-high reset signals...
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// Everyone likes active-high reset signals...
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assign async_rst = ~async_rst_n;
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assign async_rst = ~async_rst_n;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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gbuf dbg_tck_gbuf
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assign dbg_tck_o = tck_pad_i;
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(
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.CLK(tck_pad_i),
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.GL(dbg_tck_o)
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);
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`endif
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`endif
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//
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//
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// Declare synchronous reset wires here
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// Declare synchronous reset wires here
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//
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//
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// An active-low synchronous reset signal (usually a PLL lock signal)
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// An active-low synchronous reset signal (usually a PLL lock signal)
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wire sync_rst_n;
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wire sync_rst_n;
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// An active-low synchronous reset from ethernet PLL
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// An active-low synchronous reset from ethernet PLL
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wire sync_eth_rst_n;
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wire sync_eth_rst_n;
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`ifdef ACTEL_PLL
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`ifdef ACTEL_PLL
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`ifdef SYNTHESIS
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`ifdef SYNTHESIS
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wire pll_lock;
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wire pll_lock;
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wire eth_pll_lock;
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wire eth_pll_lock;
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`ifdef PLL_XTAL64_WB36
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`ifdef PLL_XTAL64_WB36
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pll_xtal64_wb36
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pll_xtal64_wb36
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`endif
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`endif
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`ifdef PLL_XTAL64_WB32
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`ifdef PLL_XTAL64_WB32
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pll_xtal64_wb32
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pll_xtal64_wb32
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`endif
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`endif
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`ifdef PLL_XTAL64_WB30
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`ifdef PLL_XTAL64_WB30
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pll_xtal64_wb30
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pll_xtal64_wb30
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`endif
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`endif
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`ifdef PLL_XTAL64_WB24
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`ifdef PLL_XTAL64_WB24
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pll_xtal64_wb24
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pll_xtal64_wb24
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`endif
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`endif
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`ifdef PLL_XTAL64_WB20
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`ifdef PLL_XTAL64_WB20
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pll_xtal64_wb20
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pll_xtal64_wb20
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`endif
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`endif
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`ifdef PLL_XTAL64_WB18
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`ifdef PLL_XTAL64_WB18
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pll_xtal64_wb18
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pll_xtal64_wb18
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`endif
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`endif
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`ifdef PLL_XTAL64_WB16
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`ifdef PLL_XTAL64_WB16
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pll_xtal64_wb16
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pll_xtal64_wb16
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`endif
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`endif
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`ifdef PLL_XTAL25_WB24
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`ifdef PLL_XTAL25_WB24
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pll_xtal25_wb24
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pll_xtal25_wb24
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`endif
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`endif
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`ifdef PLL_XTAL25_WB20
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`ifdef PLL_XTAL25_WB20
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pll_xtal25_wb20
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pll_xtal25_wb20
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`endif
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`endif
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pll0
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pll0
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(
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(
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.POWERDOWN(1'b1),
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.POWERDOWN(1'b1),
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.CLKA(sys_clk_pad_i),
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.CLKA(sys_clk_pad_i),
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.LOCK(pll_lock),
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.LOCK(pll_lock),
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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.GLA(sdram_clk_o),
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.GLA(sdram_clk_o),
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`else
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`else
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.GLA(),
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.GLA(),
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`endif
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`endif
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.GLB(wb_clk_o),
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.GLB(wb_clk_o),
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`ifdef USB_CLK
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`ifdef USB_CLK
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.GLC(usb_clk_o)
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.GLC(usb_clk_o)
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`else
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`else
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.GLC()
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.GLC()
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`endif
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`endif
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);
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);
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assign sync_rst_n = pll_lock;
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assign sync_rst_n = pll_lock;
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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`ifdef ETH_CLK_PLL
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`ifdef ETH_CLK_PLL
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eth_pll eth_pll0
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eth_pll eth_pll0
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(
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(
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.POWERDOWN(1'b1),
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.POWERDOWN(1'b1),
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.CLKA(eth_clk_pad_i),
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.CLKA(eth_clk_pad_i),
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.LOCK(eth_pll_lock),
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.LOCK(eth_pll_lock),
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.GLA(eth_clk_o)
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.GLA(eth_clk_o)
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);
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);
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`else
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`else
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// Just instantiate global buffer for incoming ethernet clock
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// Just instantiate global buffer for incoming ethernet clock
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gbuf eth_clk_gbuf
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gbuf eth_clk_gbuf
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(
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(
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.CLK(eth_clk_pad_i),
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.CLK(eth_clk_pad_i),
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.GL(eth_clk_o)
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.GL(eth_clk_o)
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);
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);
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assign eth_pll_lock = 1'b1;
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assign eth_pll_lock = 1'b1;
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`endif // !`ifdef ETH_CLK_PLL
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`endif // !`ifdef ETH_CLK_PLL
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`endif
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`endif
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assign sync_eth_rst_n = eth_pll_lock;
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assign sync_eth_rst_n = eth_pll_lock;
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`else // !`ifdef SYNTHESIS
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`else // !`ifdef SYNTHESIS
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// Buggy looking Actel PLL simulation model (it was drifting when
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// Buggy looking Actel PLL simulation model (it was drifting when
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// generating certain frequencies) so we will generate our own during
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// generating certain frequencies) so we will generate our own during
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// simulation.
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// simulation.
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reg wb_clk_gen = 0;
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reg wb_clk_gen = 0;
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reg usb_clk_gen = 0;
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reg usb_clk_gen = 0;
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// Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns
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// Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns
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parameter Tskew_actel_pll_gla = 0.200;
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parameter Tskew_actel_pll_gla = 0.200;
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assign #Tskew_actel_pll_gla sdram_clk_o = sys_clk_pad_i;
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assign #Tskew_actel_pll_gla sdram_clk_o = sys_clk_pad_i;
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always
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always
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#((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <= async_rst ? 0 : ~wb_clk_gen;
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#((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <= async_rst ? 0 : ~wb_clk_gen;
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always
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always
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#((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <= async_rst ? 0 : ~usb_clk_gen;
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#((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <= async_rst ? 0 : ~usb_clk_gen;
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assign wb_clk_o = wb_clk_gen;
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assign wb_clk_o = wb_clk_gen;
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`ifdef USB_CLK
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`ifdef USB_CLK
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assign usb_clk_o = usb_clk_gen;
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assign usb_clk_o = usb_clk_gen;
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`endif
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`endif
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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`ifdef ETH_CLK_PLL
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`ifdef ETH_CLK_PLL
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// Ethernet clock is 125MHz on ORSoC dev board
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// Ethernet clock is 125MHz on ORSoC dev board
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// PLL set to -0.06ns delay model this here
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// PLL set to -0.06ns delay model this here
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wire eth_clk, eth_clk_dly1, eth_clk_dly2;
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wire eth_clk, eth_clk_dly1, eth_clk_dly2;
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assign #3.5 eth_clk_dly1 = eth_clk_pad_i;
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assign #3.5 eth_clk_dly1 = eth_clk_pad_i;
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assign #3.5 eth_clk_dly2 = eth_clk_dly1;
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assign #3.5 eth_clk_dly2 = eth_clk_dly1;
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assign #(1 - 0.06)eth_clk = eth_clk_dly2;
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assign #(1 - 0.06)eth_clk = eth_clk_dly2;
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assign eth_clk_o = eth_clk;
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assign eth_clk_o = eth_clk;
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`else
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`else
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assign eth_clk_o = eth_clk_pad_i;
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assign eth_clk_o = eth_clk_pad_i;
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`endif // !`ifdef ETH_CLK_PLL
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`endif // !`ifdef ETH_CLK_PLL
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`endif // `ifdef ETH_CLK
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`endif // `ifdef ETH_CLK
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reg pll_lock = 0;
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reg pll_lock = 0;
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reg eth_pll_lock = 1;
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reg eth_pll_lock = 1;
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always @(async_rst)
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always @(async_rst)
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if (async_rst)
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if (async_rst)
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pll_lock = 0;
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pll_lock = 0;
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else
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else
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#300 pll_lock = 1;
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#300 pll_lock = 1;
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// Assign synchronous resets
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// Assign synchronous resets
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assign sync_rst_n = pll_lock;
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assign sync_rst_n = pll_lock;
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assign sync_eth_rst_n = eth_pll_lock;
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assign sync_eth_rst_n = eth_pll_lock;
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`endif // !`ifdef SYNTHESIS
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`endif // !`ifdef SYNTHESIS
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`endif // `ifdef ACTEL_PLL
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`endif // `ifdef ACTEL_PLL
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//
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//
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// Reset generation
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// Reset generation
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//
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//
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//
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//
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// Reset generation for wishbone
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// Reset generation for wishbone
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reg [15:0] wb_rst_shr;
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reg [15:0] wb_rst_shr;
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always @(posedge wb_clk_o or posedge async_rst)
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always @(posedge wb_clk_o or posedge async_rst)
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if (async_rst)
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if (async_rst)
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wb_rst_shr <= 16'hffff;
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wb_rst_shr <= 16'hffff;
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else
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else
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wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
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wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
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assign wb_rst_o = wb_rst_shr[15];
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assign wb_rst_o = wb_rst_shr[15];
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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// Reset generation for SDRAM controller
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// Reset generation for SDRAM controller
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reg [15:0] sdram_rst_shr;
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reg [15:0] sdram_rst_shr;
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always @(posedge sdram_clk_o or posedge async_rst)
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always @(posedge sdram_clk_o or posedge async_rst)
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if (async_rst)
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if (async_rst)
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sdram_rst_shr <= 16'hffff;
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sdram_rst_shr <= 16'hffff;
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else
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else
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sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
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sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
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assign sdram_rst_o = sdram_rst_shr[15];
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assign sdram_rst_o = sdram_rst_shr[15];
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`endif // `ifdef VERSATILE_SDRAM
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`endif // `ifdef VERSATILE_SDRAM
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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// Reset generation for ethernet SMII
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// Reset generation for ethernet SMII
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reg [15:0] eth_rst_shr;
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reg [15:0] eth_rst_shr;
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always @(posedge eth_clk_o or posedge async_rst)
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always @(posedge eth_clk_o or posedge async_rst)
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if (async_rst)
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if (async_rst)
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eth_rst_shr <= 16'hffff;
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eth_rst_shr <= 16'hffff;
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else
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else
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eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};
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eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};
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assign eth_rst_o = eth_rst_shr[15];
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assign eth_rst_o = eth_rst_shr[15];
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`endif // `ifdef ETH_CLK
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`endif // `ifdef ETH_CLK
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endmodule // clkgen
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endmodule // clkgen
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