//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// orpsoc-defines ////
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//// orpsoc-defines ////
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//// ////
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//// ////
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//// Top level ORPSoC defines file ////
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//// Top level ORPSoC defines file ////
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//// ////
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//// ////
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//// Included in toplevel and testbench ////
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//// Included in toplevel and testbench ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Uncomment a `define BOARD_XYZ to configure design RTL for it.
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// Uncomment a `define BOARD_XYZ to configure design RTL for it.
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//
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//
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// Mainly presets are for internal frequency settings, and what
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// Mainly presets are for internal frequency settings, and what
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// external oscillator is expected (ordb1's were made with various
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// external oscillator is expected (ordb1's were made with various
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// XTALs.)
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// XTALs.)
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//
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//
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// ORSoC Dev board: XTAL: 64MHz, WB: 24MHz
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// ORSoC Dev board: XTAL: 64MHz, WB: 24MHz
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//`define BOARD_ORSOC_DEV_XTAL64_WB24
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//`define BOARD_ORSOC_DEV_XTAL64_WB24
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// ORSoC Dev board: XTAL: 64MHz, WB: 20MHz
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// ORSoC Dev board: XTAL: 64MHz, WB: 20MHz
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`define BOARD_ORSOC_DEV_XTAL64_WB20
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`define BOARD_ORSOC_DEV_XTAL64_WB20
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// ORSoC Dev board: XTAL: 64MHz, WB: 18MHz
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// ORSoC Dev board: XTAL: 64MHz, WB: 18MHz
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//`define BOARD_ORSOC_DEV_XTAL64_WB18
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//`define BOARD_ORSOC_DEV_XTAL64_WB18
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// ORSoC Dev board: XTAL: 64MHz, WB: 16MHz
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// ORSoC Dev board: XTAL: 64MHz, WB: 16MHz
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//`define BOARD_ORSOC_DEV_XTAL64_WB16
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//`define BOARD_ORSOC_DEV_XTAL64_WB16
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// ORSoC Dev board: XTAL: 25MHz, WB: 24MHz
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// ORSoC Dev board: XTAL: 25MHz, WB: 24MHz
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//`define BOARD_ORSOC_DEV_XTAL25_WB24
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//`define BOARD_ORSOC_DEV_XTAL25_WB24
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// ORSoC Dev board: XTAL: 25MHz, WB: 20MHz
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// ORSoC Dev board: XTAL: 25MHz, WB: 20MHz
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//`define BOARD_ORSOC_DEV_XTAL25_WB20
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//`define BOARD_ORSOC_DEV_XTAL25_WB20
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// Actel simulation:
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// Actel simulation:
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// Clock periods are used in simulation only!
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// Clock periods are used in simulation only!
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// We generate our own because Actel's PLL model is buggy.
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// We generate our own because Actel's PLL model is buggy.
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// CLKA is SDRAM clock
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// CLKA is SDRAM clock
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// CLKB is Wishbone clock
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// CLKB is Wishbone clock
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// CLKC is USB clock
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// CLKC is USB clock
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB24
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB24
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL64_WB24
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`define PLL_XTAL64_WB24
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ETH_CLK_PLL
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`define ETH_CLK_PLL
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
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`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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`define CUSTOM_MODULES_CONFIG
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`define CUSTOM_MODULES_CONFIG
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`endif // `ifdef BOARD_ORSOC_DEV_XTAL64_WB24
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`endif // `ifdef BOARD_ORSOC_DEV_XTAL64_WB24
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB20
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB20
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL64_WB20
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`define PLL_XTAL64_WB20
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ETH_CLK_PLL
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`define ETH_CLK_PLL
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
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`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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`define CUSTOM_MODULES_CONFIG
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`define CUSTOM_MODULES_CONFIG
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`endif
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`endif
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB18
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB18
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL64_WB18
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`define PLL_XTAL64_WB18
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ETH_CLK_PLL
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`define ETH_CLK_PLL
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKB_PERIOD 55.55556 // 18 MHz
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`define ACTEL_PLL_CLKB_PERIOD 55.55556 // 18 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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`define CUSTOM_MODULES_CONFIG
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`define CUSTOM_MODULES_CONFIG
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`endif
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`endif
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB16
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`ifdef BOARD_ORSOC_DEV_XTAL64_WB16
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL64_WB16
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`define PLL_XTAL64_WB16
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ETH_CLK_PLL
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`define ETH_CLK_PLL
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
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`define ACTEL_PLL_CLKB_PERIOD 62.5 // 16 MHz
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`define ACTEL_PLL_CLKB_PERIOD 62.5 // 16 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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`define CUSTOM_MODULES_CONFIG
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`define CUSTOM_MODULES_CONFIG
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`endif
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`endif
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`ifdef BOARD_ORSOC_DEV_XTAL25_WB24
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`ifdef BOARD_ORSOC_DEV_XTAL25_WB24
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL25_WB24
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`define PLL_XTAL25_WB24
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
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`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
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`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
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`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 40 // 25 MHz
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`define BOARD_CLOCK_PERIOD 40 // 25 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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`define CUSTOM_MODULES_CONFIG
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`define CUSTOM_MODULES_CONFIG
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`endif // `ifdef BOARD_ORSOC_DEV_XTAL25_WB24
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`endif // `ifdef BOARD_ORSOC_DEV_XTAL25_WB24
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`ifdef BOARD_ORSOC_DEV_XTAL25_WB20
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`ifdef BOARD_ORSOC_DEV_XTAL25_WB20
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`define ACTEL
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`define ACTEL
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`define ACTEL_PLL
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`define ACTEL_PLL
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`define PLL_XTAL25_WB20
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`define PLL_XTAL25_WB20
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`define FPGA_BOARD_ORSOC_DEV
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`define FPGA_BOARD_ORSOC_DEV
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`define IOCONFIG_ORSOC_IO_BOARD
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`define IOCONFIG_ORSOC_IO_BOARD
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`define ETH_CLK
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`define ETH_CLK
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`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
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`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
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`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
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`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
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`define BOARD_CLOCK_PERIOD 40 // 25 MHz
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`define BOARD_CLOCK_PERIOD 40 // 25 MHz
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// Modules in system (or `define CUSTOM_CONFIG and define below)
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// `define CUSTOM_MODULES_CONFIG
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// `define CUSTOM_MODULES_CONFIG
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// Included modules: define to include
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// Included modules: define to include
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`define JTAG_DEBUG
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`define JTAG_DEBUG
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`define VERSATILE_SDRAM
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`define VERSATILE_SDRAM
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`define UART0
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`define UART0
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`define SPI0
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`define SPI0
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`define I2C0
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`define I2C0
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`define GPIO0
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`define GPIO0
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`define ETH0
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`define ETH0
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`define SMII0
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`define SMII0
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`endif
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`endif
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`ifdef CUSTOM_MODULES_CONFIG
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`ifdef CUSTOM_MODULES_CONFIG
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// Included modules: define to include
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// Included modules: define to include
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`define JTAG_DEBUG
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`define JTAG_DEBUG
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`define VERSATILE_SDRAM
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`define VERSATILE_SDRAM
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//`define RAM_WB
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//`define RAM_WB
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//`define ACTEL_UFR
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//`define ACTEL_UFR
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`define UART0
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`define UART0
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`define SPI0
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`define SPI0
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// `define SPI1
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// `define SPI1
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// `define SPI2
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// `define SPI2
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// `define I2C0
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// `define I2C0
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// `define I2C1
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// `define I2C1
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// `define I2C2
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// `define I2C2
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// `define I2C3
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// `define I2C3
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`define USB0
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`define USB0
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// `define USB1
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// `define USB1
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//`define GPIO0
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//`define GPIO0
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`define ETH0
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`define ETH0
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`define SMII0
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`define SMII0
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`define SDC_CONTROLLER
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`endif // `ifdef CUSTOM_MODULES_CONFIG
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`endif // `ifdef CUSTOM_MODULES_CONFIG
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// end of included module defines - keep this comment line here, scripts depend on it!!
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// end of included module defines - keep this comment line here, scripts depend on it!!
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`ifdef SPI0
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`ifdef SPI0
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`define SPI0_SLAVE_SELECTS
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`define SPI0_SLAVE_SELECTS
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`endif
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`endif
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`ifdef SPI1
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`ifdef SPI1
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`define SPI1_SLAVE_SELECTS
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`define SPI1_SLAVE_SELECTS
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`endif
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`endif
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`ifdef SPI2
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`ifdef SPI2
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`define SPI2_SLAVE_SELECTS
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`define SPI2_SLAVE_SELECTS
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`endif
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`endif
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`ifdef USB0
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`ifdef USB0
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// Indicate we need clock for USB
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// Indicate we need clock for USB
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`define USB_CLK
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`define USB_CLK
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// uncomment this for the module to be only a host controller
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// uncomment this for the module to be only a host controller
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`define USB0_ONLY_HOST
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`define USB0_ONLY_HOST
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`endif
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`endif
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`ifdef USB1
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`ifdef USB1
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// If we haven't already, indicate we need clock for USB
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// If we haven't already, indicate we need clock for USB
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`ifndef USB_CLK
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`ifndef USB_CLK
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`define USB_CLK
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`define USB_CLK
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`endif
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`endif
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// If both are commented out, USB1 is a host and slave otherwise uncomment
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// If both are commented out, USB1 is a host and slave otherwise uncomment
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// only one of the following to instantiate the desired type:
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// only one of the following to instantiate the desired type:
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// `define USB1_ONLY_HOST
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// `define USB1_ONLY_HOST
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`define USB1_ONLY_SLAVE
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`define USB1_ONLY_SLAVE
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`endif
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`endif
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`ifdef ETH0
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`ifdef ETH0
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// Define ETH0_PHY_RST here or where ETH0 is defined to enable an active-low
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// Define ETH0_PHY_RST here or where ETH0 is defined to enable an active-low
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// reset output to the PHY if it's possible.
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// reset output to the PHY if it's possible.
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// `define ETH0_PHY_RST
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// `define ETH0_PHY_RST
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`endif
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`endif
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`ifdef ETH_CLK
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`ifdef ETH_CLK
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// Ethernet clock rate, for simulation
|
// Ethernet clock rate, for simulation
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`define ETHERNET_CLOCK_PERIOD 8.00 // 125 MHz
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`define ETHERNET_CLOCK_PERIOD 8.00 // 125 MHz
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`endif
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`endif
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//
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//
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// Arbiter defines
|
// Arbiter defines
|
//
|
//
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|
|
// Uncomment to register things through arbiter (hopefully quicker design)
|
// Uncomment to register things through arbiter (hopefully quicker design)
|
// Instruction bus arbiter
|
// Instruction bus arbiter
|
//`define ARBITER_IBUS_REGISTERING
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//`define ARBITER_IBUS_REGISTERING
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`define ARBITER_IBUS_WATCHDOG
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`define ARBITER_IBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
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|
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// Data bus arbiter
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// Data bus arbiter
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//`define ARBITER_DBUS_REGISTERING
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//`define ARBITER_DBUS_REGISTERING
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`define ARBITER_DBUS_WATCHDOG
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`define ARBITER_DBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
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|
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// Byte bus (peripheral bus) arbiter
|
// Byte bus (peripheral bus) arbiter
|
// Don't really need the watchdog here - the databus will pick it up
|
// Don't really need the watchdog here - the databus will pick it up
|
//`define ARBITER_BYTEBUS_WATCHDOG
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//`define ARBITER_BYTEBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
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`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
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