OpenCores

Rev 408	Rev 411
Line 97...	Line 97...
`input [N:0] wptr, rptr;`	`input [N:0] wptr, rptr;`
`output reg fifo_empty;`	`output reg fifo_empty;`
`output fifo_full;`	`output fifo_full;`
`input wclk, rclk, rst;`	`input wclk, rclk, rst;`

	`ifndef GENERATE_DIRECTION_AS_LATCH
`wire direction;`	`wire direction;`
	`endif
	`ifdef GENERATE_DIRECTION_AS_LATCH
	`reg direction;`
	`endif
`reg direction_set, direction_clr;`	`reg direction_set, direction_clr;`

`wire async_empty, async_full;`	`wire async_empty, async_full;`
`wire fifo_full2;`	`wire fifo_full2;`
`reg fifo_empty2;`	`reg fifo_empty2;`
Line 296...	Line 301...
`input [(DATA_WIDTH-1):0] d_b;`	`input [(DATA_WIDTH-1):0] d_b;`
`output reg [(DATA_WIDTH-1):0] q_a;`	`output reg [(DATA_WIDTH-1):0] q_a;`
`input we_b;`	`input we_b;`
`input clk_a, clk_b;`	`input clk_a, clk_b;`
`reg [(DATA_WIDTH-1):0] q_b;`	`reg [(DATA_WIDTH-1):0] q_b;`
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;	`reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
`always @ (posedge clk_a)`	`always @ (posedge clk_a)`
`begin`	`begin`
`q_a <= ram[adr_a];`	`q_a <= ram[adr_a];`
`if (we_a)`	`if (we_a)`
`ram[adr_a] <= d_a;`	`ram[adr_a] <= d_a;`
Line 3472...	Line 3477...
`// either in this file or as command line option; +define+MT48LC16M16`	`// either in this file or as command line option; +define+MT48LC16M16`
`//`	`//`

`// Most of these defines have an effect on things in fsm_sdr_16.v`	`// Most of these defines have an effect on things in fsm_sdr_16.v`


//`define MT48LC32M16 // 64MB part	//`define MT48LC32M16 // 64MB part
`define MT48LC16M16 // 32MB part	`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part	//`define MT48LC4M16 // 8MB part

`// Define this to allow indication that a burst read is still going`	`// Define this to allow indication that a burst read is still going`
Line 3491...	Line 3495...
`// burst reading (there's no almost_empty signal from the FIFO)`	`// burst reading (there's no almost_empty signal from the FIFO)`
`define SLOW_WB_CLOCK	`define SLOW_WB_CLOCK


`ifdef MT48LC32M16	`ifdef MT48LC32M16
`// using 1 of MT48LC16M16`	`// using 1 of MT48LC32M16`
`// SDRAM data width is 16`	`// SDRAM data width is 16`

`define SDRAM_DATA_WIDTH 16	`define SDRAM_DATA_WIDTH 16
`define COL_SIZE 10	`define COL_SIZE 10
`define ROW_SIZE 13	`define ROW_SIZE 13
Line 4098...	Line 4102...
`q <= fifo_q;`	`q <= fifo_q;`


`endmodule`	`endmodule`
`endif // !`ifdef ORIGINAL_EGRESS_FIFO	`endif // !`ifdef ORIGINAL_EGRESS_FIFO
	`// true dual port RAM, sync`

	`ifdef ACTEL
	`define SYN
	`endif
`module vfifo_dual_port_ram_dc_sw`	`module vfifo_dual_port_ram_dc_sw`
`(`	`(`
`d_a,`	`d_a,`
`adr_a,`	`adr_a,`
`we_a,`	`we_a,`

Line 97...

   input [N:0]  wptr, rptr;

   input [N:0]  wptr, rptr;

   output reg   fifo_empty;

   output reg   fifo_empty;

   output       fifo_full;

   output       fifo_full;

   input        wclk, rclk, rst;

   input        wclk, rclk, rst;

`ifndef GENERATE_DIRECTION_AS_LATCH

   wire direction;

   wire direction;

`endif

`ifdef GENERATE_DIRECTION_AS_LATCH

   reg direction;

`endif

   reg  direction_set, direction_clr;

   reg  direction_set, direction_clr;

   wire async_empty, async_full;

   wire async_empty, async_full;

   wire fifo_full2;

   wire fifo_full2;

   reg  fifo_empty2;

   reg  fifo_empty2;

Line 296...

Line 301...

   input [(DATA_WIDTH-1):0]       d_b;

   input [(DATA_WIDTH-1):0]       d_b;

   output reg [(DATA_WIDTH-1):0] q_a;

   output reg [(DATA_WIDTH-1):0] q_a;

   input                         we_b;

   input                         we_b;

   input                         clk_a, clk_b;

   input                         clk_a, clk_b;

   reg [(DATA_WIDTH-1):0]         q_b;

   reg [(DATA_WIDTH-1):0]         q_b;

   reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;

   reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;

   always @ (posedge clk_a)

   always @ (posedge clk_a)

     begin

     begin

        q_a <= ram[adr_a];

        q_a <= ram[adr_a];

        if (we_a)

        if (we_a)

             ram[adr_a] <= d_a;

             ram[adr_a] <= d_a;

Line 3472...

Line 3477...

// either in this file or as command line option; +define+MT48LC16M16

// either in this file or as command line option; +define+MT48LC16M16

//

//

// Most of these defines have an effect on things in fsm_sdr_16.v

// Most of these defines have an effect on things in fsm_sdr_16.v

//`define MT48LC32M16   // 64MB part

//`define MT48LC32M16   // 64MB part

`define MT48LC16M16 // 32MB part

`define MT48LC16M16 // 32MB part

//`define MT48LC4M16  //  8MB part

//`define MT48LC4M16  //  8MB part

// Define this to allow indication that a burst read is still going

// Define this to allow indication that a burst read is still going

Line 3491...

Line 3495...

// burst reading (there's no almost_empty signal from the FIFO)

// burst reading (there's no almost_empty signal from the FIFO)

`define SLOW_WB_CLOCK

`define SLOW_WB_CLOCK

`ifdef MT48LC32M16

`ifdef MT48LC32M16

// using 1 of MT48LC16M16

// using 1 of MT48LC32M16

// SDRAM data width is 16

// SDRAM data width is 16

`define SDRAM_DATA_WIDTH 16

`define SDRAM_DATA_WIDTH 16

`define COL_SIZE 10

`define COL_SIZE 10

`define ROW_SIZE 13

`define ROW_SIZE 13

Line 4098...

Line 4102...

     q <= fifo_q;

     q <= fifo_q;

endmodule

endmodule

`endif // !`ifdef ORIGINAL_EGRESS_FIFO

`endif // !`ifdef ORIGINAL_EGRESS_FIFO

// true dual port RAM, sync

`ifdef ACTEL

        `define SYN

`endif

module vfifo_dual_port_ram_dc_sw

module vfifo_dual_port_ram_dc_sw

   d_a,

   d_a,

   adr_a,

   adr_a,

   we_a,

   we_a,

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [versatile_mem_ctrl_ip.v] - Diff between revs 408 and 411