| Line 13... |
Line 13... |
// ROM bootloader
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// ROM bootloader
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//
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//
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// Uncomment the appropriate bootloader define. This will effect the bootrom.S
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// Uncomment the appropriate bootloader define. This will effect the bootrom.S
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// file, which is compiled and converted into Verilog for inclusion at
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// file, which is compiled and converted into Verilog for inclusion at
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// synthesis time. See bootloader/bootloader.S for details on each option.
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// synthesis time. See bootloader/bootloader.S for details on each option.
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#ifndef PRELOAD_RAM
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#define BOOTROM_SPI_FLASH
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#define BOOTROM_SPI_FLASH
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//#define BOOTROM_GOTO_RESET
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//#define BOOTROM_GOTO_RESET
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//#define BOOTROM_LOOP_AT_ZERO
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//#define BOOTROM_LOOP_AT_ZERO
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//#define BOOTROM_LOOP_IN_ROM
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//#define BOOTROM_LOOP_IN_ROM
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#else
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#define BOOTROM_GOTO_RESET
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#endif
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//
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//
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// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
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// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
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//
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//
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#define SDRAM_BASE 0x0
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#define SDRAM_BASE 0x0
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| Line 89... |
Line 92... |
//
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//
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// OR1200 tick timer period define
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// OR1200 tick timer period define
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//
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//
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#define TICKS_PER_SEC 100
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#define TICKS_PER_SEC 100
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//
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// UART driver initialisation
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//
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#define UART_NUM_CORES 3
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#define UART_BASE_ADDRESSES_CSV \
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UART0_BASE, UART2_BASE, UART2_BASE
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#define UART_BAUD_RATES_CSV \
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UART0_BAUD_RATE, UART1_BAUD_RATE, UART1_BAUD_RATE
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#endif
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#endif
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No newline at end of file
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No newline at end of file
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