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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] [synplify/] [bin/] [Makefile] - Diff between revs 408 and 411

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Rev 408 Rev 411
Line 118... Line 118...
 
 
SYN_PROJ_NAME ?= $(DESIGN_NAME)
SYN_PROJ_NAME ?= $(DESIGN_NAME)
RTL_TOP ?= $(DESIGN_NAME)_top
RTL_TOP ?= $(DESIGN_NAME)_top
EDIF_FILE ?=$(RTL_TOP).edn
EDIF_FILE ?=$(RTL_TOP).edn
EDIF_FILE_OUT ?= ../out/$(EDIF_FILE)
EDIF_FILE_OUT ?= ../out/$(EDIF_FILE)
 
VLOG_NETLIST_FILE ?=$(RTL_TOP).vm
 
VLOG_NETLIST_FILE_OUT ?= ../out/$(VLOG_NETLIST_FILE)
# Synthesis params
# Synthesis params
#FREQ ?= 50.0000
#FREQ ?= 50.0000
FREQ ?= 125.000
FREQ ?= 125.000
FPGA_FAMILY ?=ProASIC3E
FPGA_FAMILY ?=ProASIC3E
#FPGA_PART ?=A3P1000
#FPGA_PART ?=A3P1000
Line 159... Line 161...
        @echo "\tRESOURCE_SHARING="$(RESOURCE_SHARING)
        @echo "\tRESOURCE_SHARING="$(RESOURCE_SHARING)
        @echo
        @echo
 
 
 
 
 
 
all: print-config $(EDIF_FILE_OUT)
all: print-config $(EDIF_FILE_OUT) $(VLOG_NETLIST_FILE_OUT)
 
 
#create the work dir
#create the work dir
$(SYN_WORK_DIR):
$(SYN_WORK_DIR):
        mkdir $(SYN_WORK_DIR)
        mkdir $(SYN_WORK_DIR)
 
 
Line 303... Line 305...
 
 
 
 
$(EDIF_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE)
$(EDIF_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE)
        cp $^ $@
        cp $^ $@
 
 
 
$(VLOG_NETLIST_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(VLOG_NETLIST_FILE)
 
        cp $^ $@
 
 
clean-all: clean-sw clean clean-edifs
clean-all: clean-sw clean clean-edifs
 
 
clean-sw:
clean-sw:
        $(MAKE) -C $(PROJECT_ROOT)/sw/lib clean-all
        $(MAKE) -C $(PROJECT_ROOT)/sw/lib clean-all
 
 

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