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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 412 and 415

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Rev 412	Rev 415
Line 204...	Line 204...
`.uart0_srx_pad_i (uart0_srx_pad_i),`	`.uart0_srx_pad_i (uart0_srx_pad_i),`
`.uart0_stx_expheader_pad_o (uart0_stx_pad_o),`	`.uart0_stx_expheader_pad_o (uart0_stx_pad_o),`
`.uart0_srx_expheader_pad_i (uart0_srx_pad_i),`	`.uart0_srx_expheader_pad_i (uart0_srx_pad_i),`
`endif	`endif
`ifdef SPI0	`ifdef SPI0
`.spi0_sck_o (spi0_sck_o),`	`/*`
	`via STARTUP_VIRTEX5`
	`.spi0_sck_o (spi0_sck_o),`
	`.spi0_miso_i (spi0_miso_i),`
	`*/`
`.spi0_mosi_o (spi0_mosi_o),`	`.spi0_mosi_o (spi0_mosi_o),`
`.spi0_miso_i (spi0_miso_i),`
`.spi0_ss_o (spi0_ss_o),`	`.spi0_ss_o (spi0_ss_o),`
`endif	`endif
`ifdef I2C0	`ifdef I2C0
`.i2c0_sda_io (i2c_sda),`	`.i2c0_sda_io (i2c_sda),`
`.i2c0_scl_io (i2c_scl),`	`.i2c0_scl_io (i2c_scl),`
Line 279...	Line 282...
`assign tms_pad_i = 1;`	`assign tms_pad_i = 1;`
`endif // !`ifdef VPI_DEBUG_ENABLE	`endif // !`ifdef VPI_DEBUG_ENABLE
`endif // `ifdef JTAG_DEBUG	`endif // `ifdef JTAG_DEBUG

`ifdef SPI0	`ifdef SPI0
	`// STARTUP_VIRTEX5 module routes these out on the board.`
	`// So for now just connect directly to the internals here.`
	`assign spi0_sck_o = dut.spi0_sck_o;`
	`assign dut.spi0_miso_i = spi0_miso_i;`

`// SPI flash memory - M25P16 compatible SPI protocol`	`// SPI flash memory - M25P16 compatible SPI protocol`
`AT26DFxxx spi0_flash`	`AT26DFxxx`
	`#(.MEMSIZE(2048*1024)) // 2MB flash on ML501`
	`spi0_flash`
`(// Outputs`	`(// Outputs`
`.SO (spi0_miso_i),`	`.SO (spi0_miso_i),`
`// Inputs`	`// Inputs`
`.CSB (spi0_ss_o),`	`.CSB (spi0_ss_o),`
`.SCK (spi0_sck_o),`	`.SCK (spi0_sck_o),`
`.SI (spi0_mosi_o),`	`.SI (spi0_mosi_o),`
`.WPB (1'b1)`	`.WPB (1'b1)`
`);`	`);`


`endif // `ifdef SPI0	`endif // `ifdef SPI0

`ifdef ETH0	`ifdef ETH0

`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`	`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`
Line 445...	Line 457...
`begin`	`begin`

`ifdef PRELOAD_RAM	`ifdef PRELOAD_RAM
`include "ddr2_model_preload.v"	`include "ddr2_model_preload.v"
`endif	`endif
	`end`

`ddr2_model u_mem0`	`ddr2_model u_mem0`
`(`	`(`
`.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),`	`.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),`
`.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),`	`.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),`
`.cke (ddr2_cke_sdram[j]),`	`.cke (ddr2_cke_sdram[j]),`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 412 and 415