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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [arbiter/] [arbiter_dbus.v] - Diff between revs 412 and 655

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Rev 412 Rev 655
Line 115... Line 115...
 
 
   wbs2_dat_o,
   wbs2_dat_o,
   wbs2_ack_o,
   wbs2_ack_o,
   wbs2_err_o,
   wbs2_err_o,
   wbs2_rty_o,
   wbs2_rty_o,
   /*
 
   // Slave four
 
   // Wishbone Slave interface
 
   wbs3_adr_i,
 
   wbs3_dat_i,
 
   wbs3_sel_i,
 
   wbs3_we_i,
 
   wbs3_cyc_i,
 
   wbs3_stb_i,
 
   wbs3_cti_i,
 
   wbs3_bte_i,
 
 
 
   wbs3_dat_o,
 
   wbs3_ack_o,
 
   wbs3_err_o,
 
   wbs3_rty_o,
 
 
 
 
   // Slave four
 
   // Wishbone Slave interface
 
   wbs3_adr_i,
 
   wbs3_dat_i,
 
   wbs3_sel_i,
 
   wbs3_we_i,
 
   wbs3_cyc_i,
 
   wbs3_stb_i,
 
   wbs3_cti_i,
 
   wbs3_bte_i,
 
 
 
   wbs3_dat_o,
 
   wbs3_ack_o,
 
   wbs3_err_o,
 
   wbs3_rty_o,
 
   /*
   // Slave five
   // Slave five
   // Wishbone Slave interface
   // Wishbone Slave interface
   wbs4_adr_i,
   wbs4_adr_i,
   wbs4_dat_i,
   wbs4_dat_i,
   wbs4_sel_i,
   wbs4_sel_i,
Line 448... Line 448...
   output [1:0]       wbs2_bte_i;
   output [1:0]       wbs2_bte_i;
   input [wb_dat_width-1:0]  wbs2_dat_o;
   input [wb_dat_width-1:0]  wbs2_dat_o;
   input                     wbs2_ack_o;
   input                     wbs2_ack_o;
   input                     wbs2_err_o;
   input                     wbs2_err_o;
   input                     wbs2_rty_o;
   input                     wbs2_rty_o;
/*
 
 
 
   // Wishbone Slave interface
 
   output [wb_adr_width-1:0] wbs3_adr_i;
 
   output [wb_dat_width-1:0] wbs3_dat_i;
 
   output [3:0]              wbs3_sel_i;
 
   output                    wbs3_we_i;
 
   output                    wbs3_cyc_i;
 
   output                    wbs3_stb_i;
 
   output [2:0]              wbs3_cti_i;
 
   output [1:0]              wbs3_bte_i;
 
   input [wb_dat_width-1:0]  wbs3_dat_o;
 
   input                     wbs3_ack_o;
 
   input                     wbs3_err_o;
 
   input                     wbs3_rty_o;
 
 
 
 
   // Wishbone Slave interface
 
   output [wb_adr_width-1:0] wbs3_adr_i;
 
   output [wb_dat_width-1:0] wbs3_dat_i;
 
   output [3:0]               wbs3_sel_i;
 
   output                    wbs3_we_i;
 
   output                    wbs3_cyc_i;
 
   output                    wbs3_stb_i;
 
   output [2:0]       wbs3_cti_i;
 
   output [1:0]       wbs3_bte_i;
 
   input [wb_dat_width-1:0]  wbs3_dat_o;
 
   input                     wbs3_ack_o;
 
   input                     wbs3_err_o;
 
   input                     wbs3_rty_o;
 
/*
 
 
   // Wishbone Slave interface
   // Wishbone Slave interface
   output [wb_adr_width-1:0] wbs4_adr_i;
   output [wb_adr_width-1:0] wbs4_adr_i;
   output [wb_dat_width-1:0] wbs4_dat_i;
   output [wb_dat_width-1:0] wbs4_dat_i;
   output [3:0]              wbs4_sel_i;
   output [3:0]              wbs4_sel_i;
Line 868... Line 868...
   wire                      wbs_rty_o_mux_i [0:wb_num_slaves-1];
   wire                      wbs_rty_o_mux_i [0:wb_num_slaves-1];
 
 
   //
   //
   // Slave selects
   // Slave selects
   //
   //
   assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here
   assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr;
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
 
   assign wb_slave_sel[2] = wbm_adr_o[31:28] == slave2_adr;
 
 
   // Auto select last slave when others are not selected
   // Auto select last slave when others are not selected
   assign wb_slave_sel[2] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]);
   assign wb_slave_sel[3] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]
 
                              | wb_slave_sel_r[2]);
 
 
/*
/*
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
 
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
   assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
   assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
   assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
   assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
   assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
   assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
Line 939... Line 940...
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel_r[0];
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel_r[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0];
 
 
 
 
   // Slave 1 inputs
   // Slave 1 inputs
   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_sel_i = wbm_sel_o;
   assign wbs1_sel_i = wbm_sel_o;
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel_r[1];
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel_r[1];
Line 954... Line 954...
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel_r[1];
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel_r[1];
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1];
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1];
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1];
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1];
 
 
 
 
   // Slave 2 inputs
   // Slave 2 inputs
   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_sel_i = wbm_sel_o;
   assign wbs2_sel_i = wbm_sel_o;
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel_r[2];
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel_r[2];
Line 968... Line 967...
   assign wbs2_bte_i = wbm_bte_o;
   assign wbs2_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
   assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
   assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2];
   assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2];
   assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2];
   assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2];
   assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2];
   assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2];
/*
 
 
 
   // Slave 3 inputs
 
   assign wbs3_adr_i = wbm_adr_o;
 
   assign wbs3_dat_i = wbm_dat_o;
 
   assign wbs3_sel_i = wbm_sel_o;
 
   assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel_r[3];
 
   assign wbs3_stb_i = wbm_stb_o & wb_slave_sel_r[3];
 
   assign wbs3_we_i =  wbm_we_o;
 
   assign wbs3_cti_i = wbm_cti_o;
 
   assign wbs3_bte_i = wbm_bte_o;
 
   assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
 
   assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3];
 
   assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3];
 
   assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3];
 
 
 
 
   // Slave 3 inputs
 
   assign wbs3_adr_i = wbm_adr_o;
 
   assign wbs3_dat_i = wbm_dat_o;
 
   assign wbs3_sel_i = wbm_sel_o;
 
   assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel_r[3];
 
   assign wbs3_stb_i = wbm_stb_o & wb_slave_sel_r[3];
 
   assign wbs3_we_i =  wbm_we_o;
 
   assign wbs3_cti_i = wbm_cti_o;
 
   assign wbs3_bte_i = wbm_bte_o;
 
   assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
 
   assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3];
 
   assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3];
 
   assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3];
 
/*
   // Slave 4 inputs
   // Slave 4 inputs
   assign wbs4_adr_i = wbm_adr_o;
   assign wbs4_adr_i = wbm_adr_o;
   assign wbs4_dat_i = wbm_dat_o;
   assign wbs4_dat_i = wbm_dat_o;
   assign wbs4_sel_i = wbm_sel_o;
   assign wbs4_sel_i = wbm_sel_o;
   assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel_r[4];
   assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel_r[4];
Line 1186... Line 1184...
 
 
   // Master out mux from slave in data
   // Master out mux from slave in data
   assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] :
   assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] :
                      wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] :
                      wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] :
                      wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] :
                      wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] :
/*                    wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
                      wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
                      wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
/*                    wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
                      wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] :
                      wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] :
                      wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] :
                      wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] :
                      wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] :
                      wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] :
                      wb_slave_sel_r[8] ? wbs_dat_o_mux_i[8] :
                      wb_slave_sel_r[8] ? wbs_dat_o_mux_i[8] :
                      wb_slave_sel_r[9] ? wbs_dat_o_mux_i[9] :
                      wb_slave_sel_r[9] ? wbs_dat_o_mux_i[9] :
Line 1206... Line 1204...
                      wbs_dat_o_mux_i[0];
                      wbs_dat_o_mux_i[0];
 
 
   // Master out acks, or together
   // Master out acks, or together
   assign wbm_ack_i = wbs_ack_o_mux_i[0] |
   assign wbm_ack_i = wbs_ack_o_mux_i[0] |
                      wbs_ack_o_mux_i[1] |
                      wbs_ack_o_mux_i[1] |
                      wbs_ack_o_mux_i[2] /*|
                      wbs_ack_o_mux_i[2] |
                      wbs_ack_o_mux_i[3] |
                      wbs_ack_o_mux_i[3] /*|
                      wbs_ack_o_mux_i[4] |
                      wbs_ack_o_mux_i[4] |
                      wbs_ack_o_mux_i[5] |
                      wbs_ack_o_mux_i[5] |
                      wbs_ack_o_mux_i[6] |
                      wbs_ack_o_mux_i[6] |
                      wbs_ack_o_mux_i[7] |
                      wbs_ack_o_mux_i[7] |
                      wbs_ack_o_mux_i[8] |
                      wbs_ack_o_mux_i[8] |
Line 1226... Line 1224...
                      ;
                      ;
 
 
 
 
   assign wbm_err_i = wbs_err_o_mux_i[0] |
   assign wbm_err_i = wbs_err_o_mux_i[0] |
                      wbs_err_o_mux_i[1] |
                      wbs_err_o_mux_i[1] |
                      wbs_err_o_mux_i[2] |/*
                      wbs_err_o_mux_i[2] |
                      wbs_err_o_mux_i[3] |
                      wbs_err_o_mux_i[3] |/*
                      wbs_err_o_mux_i[4] |
                      wbs_err_o_mux_i[4] |
                      wbs_err_o_mux_i[5] |
                      wbs_err_o_mux_i[5] |
                      wbs_err_o_mux_i[6] |
                      wbs_err_o_mux_i[6] |
                      wbs_err_o_mux_i[7] |
                      wbs_err_o_mux_i[7] |
                      wbs_err_o_mux_i[8] |
                      wbs_err_o_mux_i[8] |
Line 1246... Line 1244...
                      watchdog_err  ;
                      watchdog_err  ;
 
 
 
 
   assign wbm_rty_i = wbs_rty_o_mux_i[0] |
   assign wbm_rty_i = wbs_rty_o_mux_i[0] |
                      wbs_rty_o_mux_i[1] |
                      wbs_rty_o_mux_i[1] |
                      wbs_rty_o_mux_i[2] /*|
                      wbs_rty_o_mux_i[2] |
                      wbs_rty_o_mux_i[3] |
                      wbs_rty_o_mux_i[3] /*|
                      wbs_rty_o_mux_i[4] |
                      wbs_rty_o_mux_i[4] |
                      wbs_rty_o_mux_i[5] |
                      wbs_rty_o_mux_i[5] |
                      wbs_rty_o_mux_i[6] |
                      wbs_rty_o_mux_i[6] |
                      wbs_rty_o_mux_i[7] |
                      wbs_rty_o_mux_i[7] |
                      wbs_rty_o_mux_i[8] |
                      wbs_rty_o_mux_i[8] |

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