URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Diff between revs 503 and 655

Rev 503	Rev 655
Line 860...	Line 860...
`// Default Exception Prefix`	`// Default Exception Prefix`
`//`	`//`
`// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)`	`// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)`
`// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)`	`// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)`
`//`	`//`
`define OR1200_SR_EPH_DEF 1'b0	`define OR1200_SR_EPH_DEF 1'b1


`//`	`//`
`// FPCSR bits`	`// FPCSR bits`
`//`	`//`
Line 1812...	Line 1812...
`// //`	`// //`
`// For default reset behavior uncomment the settings under the "Boot 0x100" //`	`// For default reset behavior uncomment the settings under the "Boot 0x100" //`
`// comment below. //`	`// comment below. //`
`// //`	`// //`
`///////////////////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////////////////`
	`// Boot from 0xe0000100`
	`define OR1200_BOOT_PCREG_DEFAULT 30'h3800003f
	`define OR1200_BOOT_ADR 32'he0000100
`// Boot from 0xf0000100`	`// Boot from 0xf0000100`
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f	//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
`define OR1200_BOOT_ADR 32'hf0000100	//`define OR1200_BOOT_ADR 32'hf0000100
`// Boot from 0x100`	`// Boot from 0x100`
//`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f	//`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
//`define OR1200_BOOT_ADR 32'h00000100	//`define OR1200_BOOT_ADR 32'h00000100

`No newline at end of file`	`No newline at end of file`