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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_cpu_registers.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_cpu_registers.v,v $
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// Revision 1.6 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.5 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.4 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.3 2004/01/22 10:16:08 mohor
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// cpu_stall_o activated as soon as bp occurs.
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//
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.1 2004/01/16 14:53:33 mohor
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// *** empty log message ***
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_cpu_defines.v"
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module dbg_cpu_registers (
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data_i,
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we_i,
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tck_i,
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bp_i,
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rst_i,
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cpu_clk_i,
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ctrl_reg_o,
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cpu_stall_o,
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cpu_rst_o
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);
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input [`DBG_CPU_CTRL_LEN -1:0] data_i;
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input we_i;
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input tck_i;
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input bp_i;
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input rst_i;
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input cpu_clk_i;
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output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
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output cpu_stall_o;
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output cpu_rst_o;
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reg cpu_reset;
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wire [2:1] cpu_op_out;
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reg stall_bp, stall_bp_csff, stall_bp_tck;
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reg stall_reg, stall_reg_csff, stall_reg_cpu;
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reg cpu_reset_csff;
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reg cpu_rst_o;
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// Breakpoint is latched and synchronized. Stall is set and latched.
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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if(rst_i)
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stall_bp <= 1'b0;
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else if(bp_i)
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stall_bp <= 1'b1;
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else if(stall_reg_cpu)
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stall_bp <= 1'b0;
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end
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// Synchronizing
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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stall_bp_csff <= 1'b0;
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stall_bp_tck <= 1'b0;
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end
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else
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begin
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stall_bp_csff <= stall_bp;
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stall_bp_tck <= stall_bp_csff;
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end
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end
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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stall_reg_csff <= 1'b0;
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stall_reg_cpu <= 1'b0;
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end
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else
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begin
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stall_reg_csff <= stall_reg;
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stall_reg_cpu <= stall_reg_csff;
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end
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end
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assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
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// Writing data to the control registers (stall)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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stall_reg <= 1'b0;
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else if (stall_bp_tck)
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stall_reg <= 1'b1;
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else if (we_i)
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stall_reg <= data_i[0];
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end
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// Writing data to the control registers (reset)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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cpu_reset <= 1'b0;
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else if(we_i)
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cpu_reset <= data_i[1];
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end
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// Synchronizing signals from registers
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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cpu_reset_csff <= 1'b0;
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cpu_rst_o <= 1'b0;
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end
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else
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begin
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cpu_reset_csff <= cpu_reset;
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cpu_rst_o <= cpu_reset_csff;
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end
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end
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// Value for read back
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assign ctrl_reg_o = {cpu_reset, stall_reg};
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endmodule
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