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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_top.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_top.v,v $
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// Revision 1.45 2004/04/01 11:56:59 igorm
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// Port names and defines for the supported CPUs changed.
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//
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// Revision 1.44 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.43 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.42 2004/01/30 10:24:31 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
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// turned on.
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//
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// Revision 1.41 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.40 2004/01/20 14:23:47 mohor
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// Define name changed.
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//
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// Revision 1.39 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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//
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// Revision 1.38 2004/01/18 09:22:47 simons
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// Sensitivity list updated.
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//
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// Revision 1.37 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.36 2004/01/16 14:51:33 mohor
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// cpu registers added.
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//
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// Revision 1.35 2004/01/14 22:59:16 mohor
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// Temp version.
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//
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// Revision 1.34 2003/12/23 15:07:34 mohor
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// New directory structure. New version of the debug interface.
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// Files that are not needed removed.
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//
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// Revision 1.33 2003/10/23 16:17:01 mohor
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// CRC logic changed.
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//
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// Revision 1.32 2003/09/18 14:00:47 simons
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// Lower two address lines must be always zero.
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//
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// Revision 1.31 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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//
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// Revision 1.30 2003/08/28 13:55:22 simons
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// Three more chains added for cpu debug access.
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//
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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//
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// Revision 1.28 2002/11/06 14:22:41 mohor
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// Trst signal is not inverted here any more. Inverted on higher layer !!!.
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//
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// Revision 1.27 2002/10/10 02:42:55 mohor
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// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
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// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
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// wb_cyc_o is negated.
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//
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// Revision 1.26 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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//
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Intentional error removed.
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//
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// Revision 1.23 2002/04/17 11:16:33 mohor
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// A block for checking possible simulation/synthesis missmatch added.
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//
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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//
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// Revision 1.21 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// latched_jtag_ir used when muxing TDO instead of JTAG_IR.
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//
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Stupid bug that was entered by previous update fixed.
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//
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// Revision 1.18 2002/02/05 12:41:01 mohor
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// trst synchronization is not needed and was removed.
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//
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// Revision 1.17 2002/01/25 07:58:35 mohor
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// not filled-in. Tested in hw.
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//
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// Revision 1.16 2001/12/20 11:17:26 mohor
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// TDO and TDO Enable signal are separated into two signals.
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//
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// trst signal is synchronized to wb_clk_i.
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//
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Register length fixed.
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//
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// CRC is returned when chain selection data is transmitted.
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//
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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//
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Reset signals are not combined any more.
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//
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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//
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// Revision 1.8 2001/10/17 10:39:03 mohor
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// bs_chain_o added.
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//
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// Revision 1.7 2001/10/16 10:09:56 mohor
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// Signal names changed to lowercase.
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//
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//
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// Revision 1.6 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Asynchronous set/reset not used in trace any more.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Initial release
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_cpu_defines.v"
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// Top module
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//module dbg_top(
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module dbg_if( // Renamed by julius
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// JTAG signals
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tck_i,
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tdi_i,
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tdo_o,
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rst_i,
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// TAP states
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shift_dr_i,
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pause_dr_i,
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update_dr_i,
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// Instructions
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debug_select_i
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`ifdef DBG_WISHBONE_SUPPORTED
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// WISHBONE common signals
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,
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wb_clk_i,
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// WISHBONE master interface
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wb_adr_o,
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wb_dat_o,
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wb_dat_i,
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wb_cyc_o,
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wb_stb_o,
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wb_sel_o,
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wb_we_o,
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wb_ack_i,
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wb_cab_o,
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wb_err_i,
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wb_cti_o,
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wb_bte_o
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`endif
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`ifdef DBG_CPU0_SUPPORTED
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// CPU signals
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,
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cpu0_clk_i,
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cpu0_addr_o,
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cpu0_data_i,
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cpu0_data_o,
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cpu0_bp_i,
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cpu0_stall_o,
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cpu0_stb_o,
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cpu0_we_o,
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cpu0_ack_i,
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cpu0_rst_o
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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// CPU signals
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,
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cpu1_clk_i,
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cpu1_addr_o,
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cpu1_data_i,
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cpu1_data_o,
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cpu1_bp_i,
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cpu1_stall_o,
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cpu1_stb_o,
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cpu1_we_o,
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cpu1_ack_i,
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cpu1_rst_o
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`endif
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);
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// JTAG signals
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input tck_i;
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input tdi_i;
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output tdo_o;
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input rst_i;
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// TAP states
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input shift_dr_i;
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input pause_dr_i;
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input update_dr_i;
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// Instructions
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input debug_select_i;
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`ifdef DBG_WISHBONE_SUPPORTED
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input wb_clk_i;
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_stb_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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input wb_ack_i;
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output wb_cab_o;
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input wb_err_i;
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output [2:0] wb_cti_o;
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output [1:0] wb_bte_o;
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reg wishbone_module;
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reg wishbone_ce;
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wire tdi_wb;
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wire tdo_wb;
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wire crc_en_wb;
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wire shift_crc_wb;
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`else
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wire crc_en_wb = 1'b0;
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wire shift_crc_wb = 1'b0;
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`endif
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`ifdef DBG_CPU0_SUPPORTED
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// CPU signals
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input cpu0_clk_i;
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output [31:0] cpu0_addr_o;
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input [31:0] cpu0_data_i;
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output [31:0] cpu0_data_o;
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input cpu0_bp_i;
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output cpu0_stall_o;
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output cpu0_stb_o;
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output cpu0_we_o;
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input cpu0_ack_i;
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output cpu0_rst_o;
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reg cpu0_debug_module;
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reg cpu0_ce;
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wire cpu0_tdi;
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wire cpu0_tdo;
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wire cpu0_crc_en;
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wire cpu0_shift_crc;
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`else
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wire cpu0_crc_en = 1'b0;
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wire cpu0_shift_crc = 1'b0;
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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input cpu1_clk_i;
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output [31:0] cpu1_addr_o;
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input [31:0] cpu1_data_i;
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output [31:0] cpu1_data_o;
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input cpu1_bp_i;
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output cpu1_stall_o;
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output cpu1_stb_o;
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output cpu1_we_o;
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input cpu1_ack_i;
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output cpu1_rst_o;
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reg cpu1_debug_module;
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reg cpu1_ce;
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wire cpu1_tdi;
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wire cpu1_tdo;
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wire cpu1_crc_en;
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wire cpu1_shift_crc;
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`else
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wire cpu1_crc_en = 1'b0;
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wire cpu1_shift_crc = 1'b0;
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`endif
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reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
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reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
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reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
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reg [`DBG_TOP_MODULE_DATA_LEN -1:0] module_dr;
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reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id;
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wire module_latch_en;
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wire data_cnt_end;
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wire crc_cnt_end;
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wire status_cnt_end;
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reg crc_cnt_end_q;
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reg module_select;
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reg module_select_error;
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wire crc_out;
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wire crc_match;
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wire data_shift_en;
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wire selecting_command;
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reg tdo_o;
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wire shift_crc;
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// data counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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else if(shift_dr_i & (~data_cnt_end))
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data_cnt <= data_cnt + 1'b1;
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else if (update_dr_i)
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data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
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end
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assign data_cnt_end = data_cnt == `DBG_TOP_MODULE_DATA_LEN;
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// crc counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
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crc_cnt <= crc_cnt + 1'b1;
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else if (update_dr_i)
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crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
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end
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assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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crc_cnt_end_q <= 1'b0;
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else
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crc_cnt_end_q <= crc_cnt_end;
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end
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|
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// status counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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status_cnt <= status_cnt + 1'b1;
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else if (update_dr_i)
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status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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end
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assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
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assign selecting_command = shift_dr_i & (data_cnt == `DBG_TOP_DATA_CNT'h0) & debug_select_i;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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module_select <= 1'b0;
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else if(selecting_command & tdi_i) // Chain select
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module_select <= 1'b1;
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else if (update_dr_i)
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module_select <= 1'b0;
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end
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/* verilator lint_off COMBDLY */
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always @ (module_id)
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begin
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`ifdef DBG_CPU0_SUPPORTED
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cpu0_debug_module <= 1'b0;
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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cpu1_debug_module <= 1'b0;
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`endif
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`ifdef DBG_WISHBONE_SUPPORTED
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wishbone_module <= 1'b0;
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`endif
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module_select_error <= 1'b0;
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case (module_id) /* synthesis parallel_case */
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`ifdef DBG_CPU0_SUPPORTED
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`DBG_TOP_CPU0_DEBUG_MODULE : cpu0_debug_module <= 1'b1;
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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`DBG_TOP_CPU1_DEBUG_MODULE : cpu1_debug_module <= 1'b1;
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`endif
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`ifdef DBG_WISHBONE_SUPPORTED
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`DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= 1'b1;
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`endif
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default : module_select_error <= 1'b1;
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endcase
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end
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/* verilator lint_on COMBDLY */
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assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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module_id <= {`DBG_TOP_MODULE_ID_LENGTH{1'b1}};
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else if(module_latch_en & crc_match)
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module_id <= module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0];
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end
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assign data_shift_en = shift_dr_i & (~data_cnt_end);
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always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
module_dr <= `DBG_TOP_MODULE_DATA_LEN'h0;
|
|
else if (data_shift_en)
|
|
module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
|
|
end
|
|
|
|
|
|
// Calculating crc for input data
|
|
dbg_crc32_d1 i_dbg_crc32_d1_in
|
|
(
|
|
.data (tdi_i),
|
|
.enable (shift_dr_i),
|
|
.shift (1'b0),
|
|
.rst (rst_i),
|
|
.sync_rst (update_dr_i),
|
|
.crc_out (),
|
|
.clk (tck_i),
|
|
.crc_match (crc_match)
|
|
);
|
|
|
|
|
|
reg tdo_module_select;
|
|
wire crc_en;
|
|
wire crc_en_dbg;
|
|
reg crc_started;
|
|
|
|
assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
|
|
|
|
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
crc_started <= 1'b0;
|
|
else if (crc_en)
|
|
crc_started <= 1'b1;
|
|
else if (update_dr_i)
|
|
crc_started <= 1'b0;
|
|
end
|
|
|
|
|
|
reg tdo_tmp;
|
|
|
|
|
|
// Calculating crc for input data
|
|
dbg_crc32_d1 i_dbg_crc32_d1_out
|
|
(
|
|
.data (tdo_tmp),
|
|
.enable (crc_en), // enable has priority
|
|
// .shift (1'b0),
|
|
.shift (shift_dr_i & crc_started & (~crc_en)),
|
|
.rst (rst_i),
|
|
.sync_rst (update_dr_i),
|
|
.crc_out (crc_out),
|
|
.clk (tck_i),
|
|
.crc_match ()
|
|
);
|
|
|
|
// Following status is shifted out:
|
|
// 1. bit: 0 if crc is OK, else 1
|
|
// 2. bit: 0 if existing module_id is selected, 1 if non-existing module_id is selected
|
|
// 3. bit: 0 (always)
|
|
// 4. bit: 0 (always)
|
|
|
|
|
|
always @ (status_cnt or crc_match or module_select_error or crc_out)
|
|
begin
|
|
case (status_cnt) /* synthesis full_case parallel_case */
|
|
`DBG_TOP_STATUS_CNT_WIDTH'd0 : begin
|
|
tdo_module_select = ~crc_match;
|
|
end
|
|
`DBG_TOP_STATUS_CNT_WIDTH'd1 : begin
|
|
tdo_module_select = module_select_error;
|
|
end
|
|
`DBG_TOP_STATUS_CNT_WIDTH'd2 : begin
|
|
tdo_module_select = 1'b0;
|
|
end
|
|
`DBG_TOP_STATUS_CNT_WIDTH'd3 : begin
|
|
tdo_module_select = 1'b0;
|
|
end
|
|
`DBG_TOP_STATUS_CNT_WIDTH'd4 : begin
|
|
tdo_module_select = crc_out;
|
|
end
|
|
default : begin tdo_module_select = 1'b0; end //me added
|
|
endcase
|
|
end
|
|
|
|
|
|
|
|
|
|
assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
|
|
|
|
always @ (shift_crc or crc_out or tdo_module_select
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
or wishbone_ce or tdo_wb
|
|
`endif
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
or cpu0_ce or cpu0_tdo
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
or cpu1_ce or cpu1_tdo
|
|
`endif
|
|
)
|
|
begin
|
|
if (shift_crc) // shifting crc
|
|
tdo_tmp = crc_out;
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
else if (wishbone_ce) // shifting data from wb
|
|
tdo_tmp = tdo_wb;
|
|
`endif
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
else if (cpu0_ce) // shifting data from cpu
|
|
tdo_tmp = cpu0_tdo;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
else if (cpu1_ce) // shifting data from cpu
|
|
tdo_tmp = cpu1_tdo;
|
|
`endif
|
|
else
|
|
tdo_tmp = tdo_module_select;
|
|
end
|
|
|
|
|
|
always @ (negedge tck_i)
|
|
begin
|
|
tdo_o <= tdo_tmp;
|
|
end
|
|
|
|
|
|
|
|
|
|
// Signals for WISHBONE module
|
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
wishbone_ce <= 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
cpu0_ce <= 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
cpu1_ce <= 1'b0;
|
|
`endif
|
|
end
|
|
else if(selecting_command & (~tdi_i))
|
|
begin
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
if (wishbone_module) // wishbone CE
|
|
wishbone_ce <= 1'b1;
|
|
`endif
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
if (cpu0_debug_module) // CPU CE
|
|
cpu0_ce <= 1'b1;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
if (cpu1_debug_module) // CPU CE
|
|
cpu1_ce <= 1'b1;
|
|
`endif
|
|
end
|
|
else if (update_dr_i)
|
|
begin
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
wishbone_ce <= 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
cpu0_ce <= 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
cpu1_ce <= 1'b0;
|
|
`endif
|
|
end
|
|
end
|
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
assign tdi_wb = wishbone_ce & tdi_i;
|
|
`endif
|
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
assign cpu0_tdi = cpu0_ce & tdi_i;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
assign cpu1_tdi = cpu1_ce & tdi_i;
|
|
`endif
|
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
|
// Connecting wishbone module
|
|
dbg_wb i_dbg_wb (
|
|
// JTAG signals
|
|
.tck_i (tck_i),
|
|
.tdi_i (tdi_wb),
|
|
.tdo_o (tdo_wb),
|
|
|
|
// TAP states
|
|
.shift_dr_i (shift_dr_i),
|
|
.pause_dr_i (pause_dr_i),
|
|
.update_dr_i (update_dr_i),
|
|
|
|
.wishbone_ce_i (wishbone_ce),
|
|
.crc_match_i (crc_match),
|
|
.crc_en_o (crc_en_wb),
|
|
.shift_crc_o (shift_crc_wb),
|
|
.rst_i (rst_i),
|
|
|
|
// WISHBONE common signals
|
|
.wb_clk_i (wb_clk_i),
|
|
|
|
// WISHBONE master interface
|
|
.wb_adr_o (wb_adr_o),
|
|
.wb_dat_o (wb_dat_o),
|
|
.wb_dat_i (wb_dat_i),
|
|
.wb_cyc_o (wb_cyc_o),
|
|
.wb_stb_o (wb_stb_o),
|
|
.wb_sel_o (wb_sel_o),
|
|
.wb_we_o (wb_we_o),
|
|
.wb_ack_i (wb_ack_i),
|
|
.wb_cab_o (wb_cab_o),
|
|
.wb_err_i (wb_err_i),
|
|
.wb_cti_o (wb_cti_o),
|
|
.wb_bte_o (wb_bte_o)
|
|
);
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
|
dbg_cpu i_dbg_cpu_or1k (
|
|
// JTAG signals
|
|
.tck_i (tck_i),
|
|
.tdi_i (cpu0_tdi),
|
|
.tdo_o (cpu0_tdo),
|
|
|
|
// TAP states
|
|
.shift_dr_i (shift_dr_i),
|
|
.pause_dr_i (pause_dr_i),
|
|
.update_dr_i (update_dr_i),
|
|
|
|
.cpu_ce_i (cpu0_ce),
|
|
.crc_match_i (crc_match),
|
|
.crc_en_o (cpu0_crc_en),
|
|
.shift_crc_o (cpu0_shift_crc),
|
|
.rst_i (rst_i),
|
|
|
|
// CPU signals
|
|
.cpu_clk_i (cpu0_clk_i),
|
|
.cpu_addr_o (cpu0_addr_o),
|
|
.cpu_data_i (cpu0_data_i),
|
|
.cpu_data_o (cpu0_data_o),
|
|
.cpu_bp_i (cpu0_bp_i),
|
|
.cpu_stall_o (cpu0_stall_o),
|
|
.cpu_stb_o (cpu0_stb_o),
|
|
.cpu_we_o (cpu0_we_o),
|
|
.cpu_ack_i (cpu0_ack_i),
|
|
.cpu_rst_o (cpu0_rst_o)
|
|
);
|
|
|
|
`endif // DBG_CPU0_SUPPORTED
|
|
|
|
|
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
// Connecting cpu module
|
|
dbg_cpu i_dbg_cpu_8051 (
|
|
// JTAG signals
|
|
.tck_i (tck_i),
|
|
.tdi_i (cpu1_tdi),
|
|
.tdo_o (cpu1_tdo),
|
|
|
|
// TAP states
|
|
.shift_dr_i (shift_dr_i),
|
|
.pause_dr_i (pause_dr_i),
|
|
.update_dr_i (update_dr_i),
|
|
|
|
.cpu_ce_i (cpu1_ce),
|
|
.crc_match_i (crc_match),
|
|
.crc_en_o (cpu1_crc_en),
|
|
.shift_crc_o (cpu1_shift_crc),
|
|
.rst_i (rst_i),
|
|
|
|
// CPU signals
|
|
.cpu_clk_i (cpu1_clk_i),
|
|
.cpu_addr_o (cpu1_addr_o),
|
|
.cpu_data_i (cpu1_data_i),
|
|
.cpu_data_o (cpu1_data_o),
|
|
.cpu_bp_i (cpu1_bp_i),
|
|
.cpu_stall_o (cpu1_stall_o),
|
|
.cpu_stb_o (cpu1_stb_o),
|
|
.cpu_we_o (cpu1_we_o),
|
|
.cpu_ack_i (cpu1_ack_i),
|
|
.cpu_rst_o (cpu1_rst_o)
|
|
);
|
|
`endif
|
|
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
