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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_clockgen.v] - Diff between revs 409 and 439

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Rev 409 Rev 439
Line 87... Line 87...
wire  [7:0] CounterPreset;
wire  [7:0] CounterPreset;
wire  [7:0] TempDivider;
wire  [7:0] TempDivider;
 
 
 
 
assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1;           // We are counting half of period
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1;           // We are counting half of period
 
 
 
 
// Counter counts half period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin

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