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//////////////////////////////////////////////////////////////////////
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//// ////
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//// tap_top.v ////
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//// ////
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//// ////
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//// This file is part of the JTAG Test Access Port (TAP) ////
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//// http://www.opencores.org/projects/jtag/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2003 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: tap_top.v,v $
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// Revision 1.6 2004/01/27 10:00:33 mohor
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// Unused registers removed.
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//
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// Revision 1.5 2004/01/18 09:27:39 simons
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// Blocking non blocking assignmenst fixed.
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//
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// Revision 1.4 2004/01/17 17:37:44 mohor
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// capture_dr_o added to ports.
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//
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// Revision 1.3 2004/01/14 13:50:56 mohor
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// 5 consecutive TMS=1 causes reset of TAP.
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//
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// Revision 1.2 2004/01/08 10:29:44 mohor
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// Control signals for tdo_pad_o mux are changed to negedge.
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//
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// Revision 1.1 2003/12/23 14:52:14 mohor
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// Directory structure changed. New version of TAP.
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//
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// Revision 1.10 2003/10/23 18:08:01 mohor
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// MBIST chain connection fixed.
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//
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// Revision 1.9 2003/10/23 16:17:02 mohor
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// CRC logic changed.
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//
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// Revision 1.8 2003/10/21 09:48:31 simons
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// Mbist support added.
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//
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// Revision 1.7 2002/11/06 14:30:10 mohor
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// Trst active high. Inverted on higher layer.
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//
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// Revision 1.6 2002/04/22 12:55:56 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
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//
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// Revision 1.5 2002/03/26 14:23:38 mohor
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// Signal tdo_padoe_o changed back to tdo_padoen_o.
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//
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// Revision 1.4 2002/03/25 13:16:15 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
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// not named correctly.
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//
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// Revision 1.3 2002/03/12 14:30:05 mohor
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// Few outputs for boundary scan chain added.
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//
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// Revision 1.2 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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//
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// Revision 1.1 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "tap_defines.v"
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// Top module
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//module tap_top(
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module jtag_tap( // renamed by julius
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// JTAG pads
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tms_pad_i,
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tck_pad_i,
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trst_pad_i,
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tdi_pad_i,
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tdo_pad_o,
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tdo_padoe_o,
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// TAP states
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shift_dr_o,
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pause_dr_o,
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update_dr_o,
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capture_dr_o,
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// Select signals for boundary scan or mbist
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extest_select_o,
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sample_preload_select_o,
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mbist_select_o,
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debug_select_o,
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// TDO signal that is connected to TDI of sub-modules.
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tdo_o,
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// TDI signals from sub-modules
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debug_tdi_i, // from debug module
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bs_chain_tdi_i, // from Boundary Scan Chain
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mbist_tdi_i // from Mbist Chain
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);
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// JTAG pins
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input tms_pad_i; // JTAG test mode select pad
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input tck_pad_i; // JTAG test clock pad
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input trst_pad_i; // JTAG test reset pad
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input tdi_pad_i; // JTAG test data input pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_padoe_o; // Output enable for JTAG test data output pad
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// TAP states
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output shift_dr_o;
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output pause_dr_o;
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output update_dr_o;
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output capture_dr_o;
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// Select signals for boundary scan or mbist
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output extest_select_o;
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output sample_preload_select_o;
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output mbist_select_o;
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output debug_select_o;
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// TDO signal that is connected to TDI of sub-modules.
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output tdo_o;
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// TDI signals from sub-modules
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input debug_tdi_i; // from debug module
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input bs_chain_tdi_i; // from Boundary Scan Chain
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input mbist_tdi_i; // from Mbist Chain
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// Registers
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reg test_logic_reset;
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reg run_test_idle;
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reg select_dr_scan;
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reg capture_dr;
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reg shift_dr;
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reg exit1_dr;
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reg pause_dr;
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reg exit2_dr;
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reg update_dr;
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reg select_ir_scan;
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reg capture_ir;
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reg shift_ir, shift_ir_neg;
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reg exit1_ir;
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reg pause_ir;
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reg exit2_ir;
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reg update_ir;
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reg extest_select;
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reg sample_preload_select;
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reg idcode_select;
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reg mbist_select;
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reg debug_select;
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reg bypass_select;
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reg tdo_pad_o;
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reg tdo_padoe_o;
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reg tms_q1, tms_q2, tms_q3, tms_q4;
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wire tms_reset;
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assign tdo_o = tdi_pad_i;
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assign shift_dr_o = shift_dr;
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assign pause_dr_o = pause_dr;
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assign update_dr_o = update_dr;
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assign capture_dr_o = capture_dr;
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assign extest_select_o = extest_select;
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assign sample_preload_select_o = sample_preload_select;
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assign mbist_select_o = mbist_select;
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assign debug_select_o = debug_select;
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always @ (posedge tck_pad_i)
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begin
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tms_q1 <= tms_pad_i;
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tms_q2 <= tms_q1;
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tms_q3 <= tms_q2;
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tms_q4 <= tms_q3;
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end
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assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
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/**********************************************************************************
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* *
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* TAP State Machine: Fully JTAG compliant *
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* *
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**********************************************************************************/
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// test_logic_reset state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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test_logic_reset<= 1'b1;
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else if (tms_reset)
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test_logic_reset<= 1'b1;
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else
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begin
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if(tms_pad_i & (test_logic_reset | select_ir_scan))
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test_logic_reset<= 1'b1;
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else
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test_logic_reset<= 1'b0;
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end
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end
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// run_test_idle state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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run_test_idle<= 1'b0;
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else if (tms_reset)
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run_test_idle<= 1'b0;
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else
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if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
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run_test_idle<= 1'b1;
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else
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run_test_idle<= 1'b0;
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end
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// select_dr_scan state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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select_dr_scan<= 1'b0;
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else if (tms_reset)
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select_dr_scan<= 1'b0;
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else
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if(tms_pad_i & (run_test_idle | update_dr | update_ir))
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select_dr_scan<= 1'b1;
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else
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select_dr_scan<= 1'b0;
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end
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// capture_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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capture_dr<= 1'b0;
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else if (tms_reset)
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capture_dr<= 1'b0;
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else
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if(~tms_pad_i & select_dr_scan)
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capture_dr<= 1'b1;
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else
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capture_dr<= 1'b0;
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end
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// shift_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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shift_dr<= 1'b0;
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else if (tms_reset)
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shift_dr<= 1'b0;
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else
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if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
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shift_dr<= 1'b1;
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else
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shift_dr<= 1'b0;
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end
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// exit1_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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exit1_dr<= 1'b0;
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else if (tms_reset)
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exit1_dr<= 1'b0;
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else
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if(tms_pad_i & (capture_dr | shift_dr))
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exit1_dr<= 1'b1;
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else
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exit1_dr<= 1'b0;
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end
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// pause_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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pause_dr<= 1'b0;
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else if (tms_reset)
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pause_dr<= 1'b0;
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else
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if(~tms_pad_i & (exit1_dr | pause_dr))
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pause_dr<= 1'b1;
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else
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pause_dr<= 1'b0;
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end
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// exit2_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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exit2_dr<= 1'b0;
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else if (tms_reset)
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exit2_dr<= 1'b0;
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else
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if(tms_pad_i & pause_dr)
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exit2_dr<= 1'b1;
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else
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exit2_dr<= 1'b0;
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end
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// update_dr state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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update_dr<= 1'b0;
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else if (tms_reset)
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update_dr<= 1'b0;
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else
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if(tms_pad_i & (exit1_dr | exit2_dr))
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update_dr<= 1'b1;
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else
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update_dr<= 1'b0;
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end
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// select_ir_scan state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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select_ir_scan<= 1'b0;
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else if (tms_reset)
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select_ir_scan<= 1'b0;
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else
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if(tms_pad_i & select_dr_scan)
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select_ir_scan<= 1'b1;
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else
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select_ir_scan<= 1'b0;
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end
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// capture_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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capture_ir<= 1'b0;
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else if (tms_reset)
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capture_ir<= 1'b0;
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else
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if(~tms_pad_i & select_ir_scan)
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capture_ir<= 1'b1;
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else
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capture_ir<= 1'b0;
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end
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// shift_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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shift_ir<= 1'b0;
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else if (tms_reset)
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shift_ir<= 1'b0;
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else
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if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
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shift_ir<= 1'b1;
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else
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shift_ir<= 1'b0;
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end
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// exit1_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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exit1_ir<= 1'b0;
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else if (tms_reset)
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exit1_ir<= 1'b0;
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else
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if(tms_pad_i & (capture_ir | shift_ir))
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exit1_ir<= 1'b1;
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else
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exit1_ir<= 1'b0;
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end
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// pause_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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pause_ir<= 1'b0;
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else if (tms_reset)
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pause_ir<= 1'b0;
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else
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if(~tms_pad_i & (exit1_ir | pause_ir))
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pause_ir<= 1'b1;
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else
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pause_ir<= 1'b0;
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end
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|
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// exit2_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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exit2_ir<= 1'b0;
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else if (tms_reset)
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exit2_ir<= 1'b0;
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else
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if(tms_pad_i & pause_ir)
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exit2_ir<= 1'b1;
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else
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exit2_ir<= 1'b0;
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end
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|
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// update_ir state
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always @ (posedge tck_pad_i or posedge trst_pad_i)
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begin
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if(trst_pad_i)
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update_ir<= 1'b0;
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else if (tms_reset)
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update_ir<= 1'b0;
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else
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if(tms_pad_i & (exit1_ir | exit2_ir))
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update_ir<= 1'b1;
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else
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update_ir<= 1'b0;
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end
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|
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/**********************************************************************************
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* *
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* End: TAP State Machine *
|
|
* *
|
|
**********************************************************************************/
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|
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/**********************************************************************************
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* *
|
|
* jtag_ir: JTAG Instruction Register *
|
|
* *
|
|
**********************************************************************************/
|
|
reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
|
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reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
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reg instruction_tdo;
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|
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always @ (posedge tck_pad_i or posedge trst_pad_i)
|
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begin
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if(trst_pad_i)
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jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
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else if(capture_ir)
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jtag_ir <= 4'b0101; // This value is fixed for easier fault detection
|
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else if(shift_ir)
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jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
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end
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always @ (negedge tck_pad_i)
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begin
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instruction_tdo <= jtag_ir[0];
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end
|
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/**********************************************************************************
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* *
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* End: jtag_ir *
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* *
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|
**********************************************************************************/
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|
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/**********************************************************************************
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* *
|
|
* idcode logic *
|
|
* *
|
|
**********************************************************************************/
|
|
reg [31:0] idcode_reg;
|
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reg idcode_tdo;
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|
|
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always @ (posedge tck_pad_i)
|
|
begin
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|
if(idcode_select & shift_dr)
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|
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
|
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else
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|
idcode_reg <= `IDCODE_VALUE;
|
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end
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|
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always @ (negedge tck_pad_i)
|
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begin
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|
idcode_tdo <= idcode_reg;
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end
|
|
/**********************************************************************************
|
|
* *
|
|
* End: idcode logic *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Bypass logic *
|
|
* *
|
|
**********************************************************************************/
|
|
reg bypassed_tdo;
|
|
reg bypass_reg;
|
|
|
|
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
|
begin
|
|
if (trst_pad_i)
|
|
bypass_reg<= 1'b0;
|
|
else if(shift_dr)
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|
bypass_reg<= tdi_pad_i;
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|
end
|
|
|
|
always @ (negedge tck_pad_i)
|
|
begin
|
|
bypassed_tdo <= bypass_reg;
|
|
end
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Bypass logic *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Activating Instructions *
|
|
* *
|
|
**********************************************************************************/
|
|
// Updating jtag_ir (Instruction Register)
|
|
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
|
begin
|
|
if(trst_pad_i)
|
|
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
|
|
else if (tms_reset)
|
|
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
|
|
else if(update_ir)
|
|
latched_jtag_ir <= jtag_ir;
|
|
end
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Activating Instructions *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
// Updating jtag_ir (Instruction Register)
|
|
always @ (latched_jtag_ir)
|
|
begin
|
|
extest_select = 1'b0;
|
|
sample_preload_select = 1'b0;
|
|
idcode_select = 1'b0;
|
|
mbist_select = 1'b0;
|
|
debug_select = 1'b0;
|
|
bypass_select = 1'b0;
|
|
|
|
case(latched_jtag_ir) /* synthesis parallel_case */
|
|
`EXTEST: extest_select = 1'b1; // External test
|
|
`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
|
|
`IDCODE: idcode_select = 1'b1; // ID Code
|
|
`MBIST: mbist_select = 1'b1; // Mbist test
|
|
`DEBUG: debug_select = 1'b1; // Debug
|
|
`BYPASS: bypass_select = 1'b1; // BYPASS
|
|
default: bypass_select = 1'b1; // BYPASS
|
|
endcase
|
|
end
|
|
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Multiplexing TDO data *
|
|
* *
|
|
**********************************************************************************/
|
|
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
|
|
debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
|
|
bypassed_tdo)
|
|
begin
|
|
if(shift_ir_neg)
|
|
tdo_pad_o = instruction_tdo;
|
|
else
|
|
begin
|
|
case(latched_jtag_ir_neg) // synthesis parallel_case
|
|
`IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
|
|
`DEBUG: tdo_pad_o = debug_tdi_i; // Debug
|
|
`SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
|
|
`EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
|
|
`MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
|
|
default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
// Tristate control for tdo_pad_o pin
|
|
always @ (negedge tck_pad_i)
|
|
begin
|
|
tdo_padoe_o <= shift_ir | shift_dr | (pause_dr & debug_select);
|
|
end
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Multiplexing TDO data *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
always @ (negedge tck_pad_i)
|
|
begin
|
|
shift_ir_neg <= shift_ir;
|
|
latched_jtag_ir_neg <= latched_jtag_ir;
|
|
end
|
|
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
