OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ctrl.v] - Diff between revs 363 and 403

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 363 Rev 403
Line 60... Line 60...
   // Internal i/f
   // Internal i/f
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
   wb_flushpipe,
   wb_flushpipe,
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op,
   rf_addrw, rfwb_op, fpu_op,
   comp_op, rf_addrw, rfwb_op, fpu_op,
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
   sel_b, id_lsu_op,
   sel_b, id_lsu_op,
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
Line 98... Line 98...
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output                                  rf_rda;
output                                  rf_rda;
output                                  rf_rdb;
output                                  rf_rdb;
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
 
output [`OR1200_ALUOP2_WIDTH-1:0]                alu_op2;
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
input                                   pc_we;
input                                   pc_we;
Line 142... Line 143...
// Internal wires and regs
// Internal wires and regs
//
//
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
 
reg [`OR1200_ALUOP2_WIDTH-1:0]                   alu_op2;
wire                                    if_maci_op;
wire                                    if_maci_op;
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
Line 748... Line 750...
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
`else
`else
                | (id_insn[3:0] == `OR1200_ALUOP_ADDC)
                | (id_insn[3:0] == `OR1200_ALUOP_ADDC)
`endif
`endif
 
 
 
`ifdef OR1200_IMPL_ALU_FFL1
 
`else
 
                | (id_insn[3:0] == `OR1200_ALUOP_FFL1)
 
`endif
 
 
`ifdef OR1200_IMPL_ALU_ROTATE
`ifdef OR1200_IMPL_ALU_ROTATE
`else
`else
                | ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
                | ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
                   (id_insn[7:6] == `OR1200_SHROTOP_ROR))
                   (id_insn[7:6] == `OR1200_SHROTOP_ROR))
`endif
`endif
Line 842... Line 849...
          endcase
          endcase
 
 
        end
        end
end
end
 
 
 
 
 
//
 
// Decode of alu_op2 (field of bits 9:8)
 
//
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
 
        if (rst == `OR1200_RST_VALUE)
 
                alu_op2 <=  0;
 
        else if (!ex_freeze & id_freeze | ex_flushpipe)
 
                alu_op2 <= 0;
 
        else if (!ex_freeze) begin
 
                alu_op2 <=  id_insn[`OR1200_ALUOP2_POS];
 
        end
 
end
 
 
 
 
//
//
// Decode of spr_read, spr_write
// Decode of spr_read, spr_write
//
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
        if (rst == `OR1200_RST_VALUE) begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.