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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wb_biu.v] - Diff between revs 477 and 479

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Rev 477 Rev 479
Line 233... Line 233...
        wb_fsm_trans : begin
        wb_fsm_trans : begin
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
                        !(wb_ack & wb_cti_o == 3'b111);
                        !(wb_ack & wb_cti_o == 3'b111);
 
 
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 ;
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
           wb_cti_nxt[1] = 1'b1  ;
           wb_cti_nxt[1] = 1'b1  ;
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
 
 
 
 
           //if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010  | 
 
           //     biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
 
 
 
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
             wb_fsm_state_nxt = wb_fsm_last;
             wb_fsm_state_nxt = wb_fsm_last;
           else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
           else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
                    wb_stb_o)
                    wb_stb_o)
Line 296... Line 292...
         wb_dat_o       <=  {dw{1'b0}};
         wb_dat_o       <=  {dw{1'b0}};
`endif
`endif
      end
      end
      else begin
      else begin
         wb_cyc_o       <=  wb_cyc_nxt;
         wb_cyc_o       <=  wb_cyc_nxt;
         //             wb_stb_o        <=  wb_stb_nxt;
 
         if (wb_ack & wb_cti_o == 3'b111)
         if (wb_ack & wb_cti_o == 3'b111)
           wb_stb_o        <=  1'b0;
           wb_stb_o        <=  1'b0;
         else
         else
           wb_stb_o        <=  wb_stb_nxt;
           wb_stb_o        <=  wb_stb_nxt;
 
`ifndef OR1200_NO_BURSTS
         wb_cti_o       <=  wb_cti_nxt;
         wb_cti_o       <=  wb_cti_nxt;
 
`endif
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
         wb_cab_o       <=  biu_cab_i;
         wb_cab_o       <=  biu_cab_i;
`endif
`endif
         // we and sel - set at beginning of access 
         // we and sel - set at beginning of access 

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