| Line 70... |
Line 70... |
////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Wires
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// Wires
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//
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//
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wire async_rst;
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wire wb_clk, wb_rst;
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wire wb_clk, wb_rst;
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wire dbg_tck;
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wire dbg_tck;
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clkgen clkgen0
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clkgen clkgen0
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(
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(
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.clk_pad_i (clk_pad_i),
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.clk_pad_i (clk_pad_i),
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.async_rst_o (async_rst),
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.wb_clk_o (wb_clk),
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.wb_clk_o (wb_clk),
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.wb_rst_o (wb_rst),
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.wb_rst_o (wb_rst),
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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.tck_pad_i (tck_pad_i),
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.tck_pad_i (tck_pad_i),
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| Line 427... |
Line 430... |
//
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//
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wire dbg_if_select;
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wire dbg_if_select;
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wire dbg_if_tdo;
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wire dbg_if_tdo;
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wire jtag_tap_tdo;
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wire jtag_tap_tdo;
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wire jtag_tap_shift_dr, jtag_tap_pause_dr,
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wire jtag_tap_shift_dr, jtag_tap_pause_dr,
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jtag_tap_upate_dr, jtag_tap_capture_dr;
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jtag_tap_update_dr, jtag_tap_capture_dr;
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//
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//
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// Instantiation
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// Instantiation
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//
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//
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jtag_tap jtag_tap0
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jtag_tap jtag_tap0
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| Line 441... |
Line 444... |
.tms_pad_i (tms_pad_i),
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.tms_pad_i (tms_pad_i),
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.tck_pad_i (dbg_tck),
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.tck_pad_i (dbg_tck),
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.trst_pad_i (async_rst),
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.trst_pad_i (async_rst),
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.tdi_pad_i (tdi_pad_i),
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.tdi_pad_i (tdi_pad_i),
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.tdo_padoe_o (tdo_padoe_o),
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.tdo_padoe_o (),
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.tdo_o (jtag_tap_tdo),
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.tdo_o (jtag_tap_tdo),
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.shift_dr_o (jtag_tap_shift_dr),
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.shift_dr_o (jtag_tap_shift_dr),
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.pause_dr_o (jtag_tap_pause_dr),
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.pause_dr_o (jtag_tap_pause_dr),
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| Line 690... |
Line 693... |
// Generic main RAM
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// Generic main RAM
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//
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//
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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parameter wb_ram_dat_width = 32;
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parameter wb_ram_dat_width = 32;
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parameter wb_ram_adr_width = 25;
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parameter wb_ram_adr_width = 23;
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//parameter ram_wb_mem_size = 2097152; // 8MB
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//parameter ram_wb_mem_size = 2097152; // 8MB
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parameter wb_ram_mem_size = 8388608; // 32MB -- for linux test
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parameter wb_ram_mem_size = 8388608; // 32MB -- for linux test
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// Arbiter logic for sharing the RAM between 2 masters
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// Arbiter logic for sharing the RAM between 2 masters
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| Line 744... |
Line 747... |
wb_ram_last_selected <= 2'b01;
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wb_ram_last_selected <= 2'b01;
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else if (!(&wb_ram_mast_select) & wbs_i_mc0_cyc_i & wb_ram_arb_for_ibus)
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else if (!(&wb_ram_mast_select) & wbs_i_mc0_cyc_i & wb_ram_arb_for_ibus)
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wb_ram_last_selected <= 2'b10;
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wb_ram_last_selected <= 2'b10;
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// Mux input signals to RAM (default to wbs_d_mc0)
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// Mux input signals to RAM (default to wbs_d_mc0)
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assign wb_ram_adr_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_adr_i :
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assign wb_ram_adr_i = (wb_ram_mast_select[1]) ?
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(wb_ram_mast_select[0]) ? wbs_d_mc0_adr_i : 0;
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wbs_i_mc0_adr_i[wb_ram_adr_width-1:0] :
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(wb_ram_mast_select[0]) ?
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wbs_d_mc0_adr_i[wb_ram_adr_width-1:0] : 0;
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assign wb_ram_bte_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_bte_i :
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assign wb_ram_bte_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_bte_i :
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(wb_ram_mast_select[0]) ? wbs_d_mc0_bte_i : 0;
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(wb_ram_mast_select[0]) ? wbs_d_mc0_bte_i : 0;
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assign wb_ram_cti_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cti_i :
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assign wb_ram_cti_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cti_i :
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(wb_ram_mast_select[0]) ? wbs_d_mc0_cti_i : 0;
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(wb_ram_mast_select[0]) ? wbs_d_mc0_cti_i : 0;
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assign wb_ram_cyc_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cyc_i :
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assign wb_ram_cyc_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cyc_i :
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