| Line 230... |
Line 230... |
wire wbs_d_uart0_ack_o;
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wire wbs_d_uart0_ack_o;
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wire wbs_d_uart0_err_o;
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wire wbs_d_uart0_err_o;
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wire wbs_d_uart0_rty_o;
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wire wbs_d_uart0_rty_o;
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// intgen wires
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wire [31:0] wbs_d_intgen_adr_i;
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wire [7:0] wbs_d_intgen_dat_i;
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wire [3:0] wbs_d_intgen_sel_i;
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wire wbs_d_intgen_we_i;
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wire wbs_d_intgen_cyc_i;
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wire wbs_d_intgen_stb_i;
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wire [2:0] wbs_d_intgen_cti_i;
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wire [1:0] wbs_d_intgen_bte_i;
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wire [7:0] wbs_d_intgen_dat_o;
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wire wbs_d_intgen_ack_o;
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wire wbs_d_intgen_err_o;
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wire wbs_d_intgen_rty_o;
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//
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//
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// Wishbone instruction bus arbiter
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// Wishbone instruction bus arbiter
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//
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//
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arbiter_ibus arbiter_ibus0
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arbiter_ibus arbiter_ibus0
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| Line 406... |
Line 421... |
.wbs0_dat_o (wbs_d_uart0_dat_o),
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.wbs0_dat_o (wbs_d_uart0_dat_o),
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.wbs0_ack_o (wbs_d_uart0_ack_o),
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.wbs0_ack_o (wbs_d_uart0_ack_o),
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.wbs0_err_o (wbs_d_uart0_err_o),
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.wbs0_err_o (wbs_d_uart0_err_o),
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.wbs0_rty_o (wbs_d_uart0_rty_o),
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.wbs0_rty_o (wbs_d_uart0_rty_o),
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.wbs1_adr_i (wbs_d_intgen_adr_i),
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.wbs1_dat_i (wbs_d_intgen_dat_i),
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.wbs1_we_i (wbs_d_intgen_we_i),
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.wbs1_cyc_i (wbs_d_intgen_cyc_i),
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.wbs1_stb_i (wbs_d_intgen_stb_i),
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.wbs1_cti_i (wbs_d_intgen_cti_i),
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.wbs1_bte_i (wbs_d_intgen_bte_i),
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.wbs1_dat_o (wbs_d_intgen_dat_o),
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.wbs1_ack_o (wbs_d_intgen_ack_o),
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.wbs1_err_o (wbs_d_intgen_err_o),
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.wbs1_rty_o (wbs_d_intgen_rty_o),
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// Clock, reset inputs
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// Clock, reset inputs
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.wb_clk (wb_clk),
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.wb_clk (wb_clk),
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.wb_rst (wb_rst));
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.wb_rst (wb_rst));
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defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
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defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
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| Line 810... |
Line 837... |
assign wbs_d_uart0_dat_o = 0;
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assign wbs_d_uart0_dat_o = 0;
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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`endif // !`ifdef UART0
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`endif // !`ifdef UART0
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`ifdef INTGEN
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|
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wire intgen_irq;
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|
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intgen intgen0
|
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(
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.clk_i (wb_clk),
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.rst_i (wb_rst),
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.wb_adr_i (wbs_d_intgen_adr_i[intgen_addr_width-1:0]),
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.wb_cyc_i (wbs_d_intgen_cyc_i),
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.wb_stb_i (wbs_d_intgen_stb_i),
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.wb_dat_i (wbs_d_intgen_dat_i),
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.wb_we_i (wbs_d_intgen_we_i),
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.wb_ack_o (wbs_d_intgen_ack_o),
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.wb_dat_o (wbs_d_intgen_dat_o),
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|
|
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.irq_o (intgen_irq)
|
|
);
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|
|
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`endif // `ifdef INTGEN
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assign wbs_d_intgen_err_o = 0;
|
|
assign wbs_d_intgen_rty_o = 0;
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// OR1200 Interrupt assignment
|
// OR1200 Interrupt assignment
|
//
|
//
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
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| Line 843... |
Line 894... |
assign or1200_pic_ints[14] = 0;
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assign or1200_pic_ints[14] = 0;
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assign or1200_pic_ints[15] = 0;
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assign or1200_pic_ints[15] = 0;
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assign or1200_pic_ints[16] = 0;
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assign or1200_pic_ints[16] = 0;
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assign or1200_pic_ints[17] = 0;
|
assign or1200_pic_ints[17] = 0;
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assign or1200_pic_ints[18] = 0;
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assign or1200_pic_ints[18] = 0;
|
|
`ifdef INTGEN
|
|
assign or1200_pic_ints[19] = intgen_irq;
|
|
`else
|
assign or1200_pic_ints[19] = 0;
|
assign or1200_pic_ints[19] = 0;
|
|
`endif
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|
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endmodule // top
|
endmodule // top
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|
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// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../arbiter" "../uart16550" "../or1200" "../dbg_if" "../jtag_tap" "../rom" "../simple_spi" )
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// verilog-library-directories:("." "../arbiter" "../uart16550" "../or1200" "../dbg_if" "../jtag_tap" "../rom" "../simple_spi" )
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