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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [Makefile.inc] - Diff between revs 349 and 360

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Rev 349 Rev 360
Line 27... Line 27...
#### Public License along with this source; if not, download it   ####
#### Public License along with this source; if not, download it   ####
#### from http://www.opencores.org/lgpl.shtml                     ####
#### from http://www.opencores.org/lgpl.shtml                     ####
####                                                              ####
####                                                              ####
######################################################################
######################################################################
 
 
DESIGN_NAME=design
DESIGN_NAME=orpsoc
 
 
OR32_TOOL_PREFIX=or32-elf-
OR32_TOOL_PREFIX=or32-elf-
 
 
OR32_LD=$(OR32_TOOL_PREFIX)ld
OR32_LD=$(OR32_TOOL_PREFIX)ld
OR32_AS=$(OR32_TOOL_PREFIX)as
OR32_AS=$(OR32_TOOL_PREFIX)as
Line 59... Line 59...
 
 
OR32_CFLAGS ?=-g -nostdlib -O2 -I../include $(MARCH_FLAGS)
OR32_CFLAGS ?=-g -nostdlib -O2 -I../include $(MARCH_FLAGS)
OR32_LDFLAGS ?=-lgcc -T../support/or32.ld -e 256
OR32_LDFLAGS ?=-lgcc -T../support/or32.ld -e 256
 
 
# This path must be correct!
# This path must be correct!
# Currently no overall design defines file - to come!
DESIGN_VERILOG_DEFINES=../../rtl/verilog/include/$(DESIGN_NAME)-defines.v
#DESIGN_VERILOG_DEFINES=../../rtl/verilog/include/$(DESIGN_NAME)-defines.v
DESIGN_PROCESSED_VERILOG_DEFINES=../include/$(DESIGN_NAME)-defines.h
#DESIGN_PROCESSED_VERILOG_DEFINES=../include/$(DESIGN_NAME)-defines.h
 
 
 
OR1200_VERILOG_DEFINES=../../rtl/verilog/or1200_defines.v
OR1200_VERILOG_DEFINES=../../rtl/verilog/include/or1200_defines.v
OR1200_PROCESSED_VERILOG_DEFINES=../include/or1200-defines.h
OR1200_PROCESSED_VERILOG_DEFINES=../include/or1200-defines.h
 
 
#PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
#PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
PROCESSED_DEFINES= $(OR1200_PROCESSED_VERILOG_DEFINES)
PROCESSED_DEFINES= $(OR1200_PROCESSED_VERILOG_DEFINES)
 
 

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