| Line 6... |
Line 6... |
//// Transmits packets, testing both 100mbit and 10mbit modes. ////
|
//// Transmits packets, testing both 100mbit and 10mbit modes. ////
|
//// Expects testbench to be checking each packet sent. ////
|
//// Expects testbench to be checking each packet sent. ////
|
//// Define, ETH_TX_TEST_LENGTH, set further down, controls how ////
|
//// Define, ETH_TX_TEST_LENGTH, set further down, controls how ////
|
//// many packets the test will send. ////
|
//// many packets the test will send. ////
|
//// ////
|
//// ////
|
//// Test data comes from pre-calculated array of random values, ////
|
|
//// MAC TX buffer pointers are set to addresses in this array, ////
|
|
//// saving copying the data around before transfers. ////
|
|
//// ////
|
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
|
//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
|
//// open_eth driver. ////
|
//// open_eth driver. ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
| Line 42... |
Line 38... |
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
#include "or32-utils.h"
|
#include "cpu-utils.h"
|
#include "spr-defs.h"
|
|
#include "board.h"
|
#include "board.h"
|
#include "int.h"
|
#include "int.h"
|
#include "uart.h"
|
#include "ethmac.h"
|
#include "open-eth.h"
|
|
#include "printf.h"
|
|
#include "eth-phy-mii.h"
|
#include "eth-phy-mii.h"
|
|
|
volatile unsigned tx_done;
|
volatile unsigned tx_done;
|
volatile unsigned rx_done;
|
volatile unsigned rx_done;
|
static int next_tx_buf_num;
|
static int next_tx_buf_num;
|
| Line 62... |
Line 55... |
/* Interrupt functions */
|
/* Interrupt functions */
|
void oeth_interrupt(void);
|
void oeth_interrupt(void);
|
static void oeth_rx(void);
|
static void oeth_rx(void);
|
static void oeth_tx(void);
|
static void oeth_tx(void);
|
|
|
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
|
|
#define RTLSIM
|
|
|
|
#ifdef RTLSIM
|
|
#define printk
|
|
#else
|
|
#define printk printf
|
|
#endif
|
|
/* Let the ethernet packets use a space beginning here for buffering */
|
/* Let the ethernet packets use a space beginning here for buffering */
|
#define ETH_BUFF_BASE 0x01000000
|
#define ETH_BUFF_BASE 0x01000000
|
|
|
|
|
#define RXBUFF_PREALLOC 1
|
#define RXBUFF_PREALLOC 1
|
#define TXBUFF_PREALLOC 1
|
#define TXBUFF_PREALLOC 1
|
//#undef RXBUFF_PREALLOC
|
//#undef RXBUFF_PREALLOC
|
//#undef TXBUFF_PREALLOC
|
//#undef TXBUFF_PREALLOC
|
|
|
| Line 95... |
Line 79... |
/* Buffer size
|
/* Buffer size
|
*/
|
*/
|
#define OETH_RX_BUFF_SIZE 0x600 - 4
|
#define OETH_RX_BUFF_SIZE 0x600 - 4
|
#define OETH_TX_BUFF_SIZE 0x600 - 4
|
#define OETH_TX_BUFF_SIZE 0x600 - 4
|
|
|
/* OR32 Page size def */
|
|
#define PAGE_SHIFT 13
|
|
#define PAGE_SIZE (1UL << PAGE_SHIFT)
|
|
|
|
/* How many buffers per page
|
|
*/
|
|
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
|
|
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
|
|
|
|
/* How many pages is needed for buffers
|
|
*/
|
|
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
|
|
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
|
|
|
|
/* Buffer size (if not XXBUF_PREALLOC
|
/* Buffer size (if not XXBUF_PREALLOC
|
*/
|
*/
|
#define MAX_FRAME_SIZE 1518
|
#define MAX_FRAME_SIZE 1518
|
|
|
/* The buffer descriptors track the ring buffers.
|
/* The buffer descriptors track the ring buffers.
|
*/
|
*/
|
struct oeth_private {
|
struct oeth_private {
|
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
|
|
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
|
|
|
|
unsigned short tx_next; /* Next buffer to be sent */
|
unsigned short tx_next; /* Next buffer to be sent */
|
unsigned short tx_last; /* Next buffer to be checked if packet sent */
|
unsigned short tx_last; /* Next buffer to be checked if packet sent */
|
unsigned short tx_full; /* Buffer ring fuul indicator */
|
unsigned short tx_full; /* Buffer ring fuul indicator */
|
unsigned short rx_cur; /* Next buffer to be checked if packet received */
|
unsigned short rx_cur; /* Next buffer to check if packet received */
|
|
|
oeth_regs *regs; /* Address of controller registers. */
|
oeth_regs *regs; /* Address of controller registers. */
|
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
|
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
|
oeth_bd *tx_bd_base; /* Address of Tx BDs. */
|
oeth_bd *tx_bd_base; /* Address of Tx BDs. */
|
|
|
// struct net_device_stats stats;
|
// struct net_device_stats stats;
|
};
|
};
|
|
|
|
|
// Data array of data to transmit, tx_data_array[]
|
// Data array of data to transmit, tx_data_array[]
|
#include "eth-rxtx-data.h"
|
// Not included in ORPSoC - #include "eth-rxtx-data.h"
|
int tx_data_pointer;
|
//int tx_data_pointer;
|
|
|
#define PHYNUM 7
|
#define PHYNUM 7
|
|
|
void
|
void
|
eth_mii_write(char phynum, short regnum, short data)
|
eth_mii_write(char phynum, short regnum, short data)
|
| Line 398... |
Line 366... |
|
|
return;
|
return;
|
|
|
}
|
}
|
|
|
/* enable RX, loop waiting for arrived packets and print them out */
|
|
void oeth_monitor_rx(void)
|
|
{
|
|
volatile oeth_regs *regs;
|
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
|
/* Set RXEN in MAC MODER */
|
|
regs->moder = OETH_MODER_RXEN | regs->moder;
|
|
|
|
|
|
volatile oeth_bd *rx_bd;
|
|
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
|
|
|
|
volatile int i;
|
|
|
|
while (1)
|
|
{
|
|
|
|
for(i=0;i<OETH_RXBD_NUM;i++)
|
|
{
|
|
if (!(rx_bd[i].len_status & OETH_RX_BD_EMPTY)) /* Not empty */
|
|
{
|
|
// Something in this buffer!
|
|
printk("Oeth: RX in buf %d - len_status: 0x%lx\n",i, rx_bd[i].len_status);
|
|
/* Clear recieved bit */
|
|
rx_bd[i].len_status |= OETH_RX_BD_EMPTY;
|
|
printk("\t end of packet\n\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
char broadcast_ping_packet[] = {
|
|
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
|
|
0x08,0x00,
|
|
0x45,
|
|
0x00,
|
|
0x00,0x54,
|
|
0x00,0x00,
|
|
0x40,
|
|
0x00,
|
|
0x40,
|
|
0x01,
|
|
0xef,0xef,
|
|
0xc0,0xa8,0x64,0x58, /* Source IP */
|
|
0xc0,0xa8,0x64,0xff, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0x68,0x25,0xa5,0x4a,0xcf,0x05,0x0c,0x00,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37};
|
|
|
|
|
|
char big_broadcast_ping_packet[] = {
|
|
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
|
|
0x08,0x00,
|
|
0x45,
|
|
0x00,
|
|
// 0x00,0x54, /* length */
|
|
0x05,0x1c, /* length */
|
|
0x00,0x00,
|
|
0x40,
|
|
0x00,
|
|
0x40,
|
|
0x01,
|
|
0xee,0xf5,
|
|
0xc0,0xa8,0x64,0x9b, /* Source IP */
|
|
0xc0,0xa8,0x64,0xff, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255};
|
|
|
|
|
|
/* This should be 98 bytes big */
|
|
char ping_packet[] = {
|
|
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/
|
|
//0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /*DST MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
|
|
0x08, 0x00, /*TYPE*/
|
|
/* IP */
|
|
0x45, /* Version, header length*/
|
|
0x00, /* Differentiated services field */
|
|
0x00, 0x54, /* Total length */
|
|
0x00, 0x00, /* Identification */
|
|
0x40, /* Flags */
|
|
0x00, /* Fragment offset */
|
|
0x40, /* Time to live */
|
|
0x01, /* Protocol (0x01 = ICMP */
|
|
0xef, 0xf3, /* Header checksum */
|
|
//0xc0, 0xa8, 0x64, 0xDE, /* Source IP */
|
|
0xc0, 0xa8, 0x0, 0x58, /* Source IP */
|
|
//0xa, 0x1, 0x1, 0x3, /* Source IP */
|
|
0xc0, 0xa8, 0x64, 0x69, /* Dest. IP */
|
|
0xc0, 0xa8, 0x0, 0xb, /* Dest. IP */
|
|
//0xa, 0x1, 0x1, 0x1, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08, 0x00, 0x9a, 0xd4, 0xc8, 0x18, 0x00, 0x01, 0xd9, 0x8c, 0x54,
|
|
0x4a, 0x7b, 0x37, 0x01, 0x00, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,
|
|
0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
|
|
0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
|
|
0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e,
|
|
0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37
|
|
};
|
|
|
|
|
|
/* The interrupt handler.
|
/* The interrupt handler.
|
*/
|
*/
|
void
|
void
|
oeth_interrupt(void)
|
oeth_interrupt(void)
|
{
|
{
|
| Line 586... |
Line 386... |
*/
|
*/
|
int_events = regs->int_src;
|
int_events = regs->int_src;
|
regs->int_src = int_events;
|
regs->int_src = int_events;
|
|
|
|
|
#ifndef RTLSIM
|
|
printk(".");
|
|
|
|
printk("\n=tx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
|
|
((oeth_bd *)(OETH_BD_BASE))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+8))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+16))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+24))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+32))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+40))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+48))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+56))->len_status);
|
|
|
|
printk("=rx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
|
|
((oeth_bd *)(OETH_BD_BASE+64))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+8))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+16))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+24))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+32))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+40))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+48))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+56))->len_status);
|
|
|
|
printk("=int | txb %d | txe %d | rxb %d | rxe %d | busy %d\n",
|
|
(int_events & OETH_INT_TXB) > 0,
|
|
(int_events & OETH_INT_TXE) > 0,
|
|
(int_events & OETH_INT_RXF) > 0,
|
|
(int_events & OETH_INT_RXE) > 0,
|
|
(int_events & OETH_INT_BUSY) > 0);
|
|
#endif
|
|
|
|
|
|
|
|
/* Handle receive event in its own function.
|
/* Handle receive event in its own function.
|
*/
|
*/
|
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
|
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
|
serviced |= 0x1;
|
serviced |= 0x1;
|
oeth_rx();
|
oeth_rx();
|
| Line 640... |
Line 407... |
/* Check for receive busy, i.e. packets coming but no place to
|
/* Check for receive busy, i.e. packets coming but no place to
|
* put them.
|
* put them.
|
*/
|
*/
|
if (int_events & OETH_INT_BUSY) {
|
if (int_events & OETH_INT_BUSY) {
|
serviced |= 0x4;
|
serviced |= 0x4;
|
#ifndef RTLSIM
|
|
printk("b");
|
|
#endif
|
|
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
|
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
|
oeth_rx();
|
oeth_rx();
|
}
|
}
|
|
|
|
|
#if 0
|
|
if (serviced == 0) {
|
|
void die(const char * str, struct pt_regs * regs, long err);
|
|
int show_stack(unsigned long *esp);
|
|
printk("!");
|
|
// printk("unserviced irq\n");
|
|
// show_stack(NULL);
|
|
// die("unserviced irq\n", regs, 801);
|
|
}
|
|
#endif
|
|
|
|
if (serviced == 0)
|
|
printk("\neth interrupt called but nothing serviced\n");
|
|
|
|
else /* Something happened ... either RX or TX */
|
|
printk(" | serviced 0x%x\n", serviced);
|
|
|
|
return;
|
return;
|
}
|
}
|
|
|
|
|
|
|
| Line 682... |
Line 428... |
int pkt_len, i;
|
int pkt_len, i;
|
int bad = 0;
|
int bad = 0;
|
|
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
|
|
|
printk("r");
|
|
|
|
|
|
/* Find RX buffers marked as having received data */
|
/* Find RX buffers marked as having received data */
|
for(i = 0; i < OETH_RXBD_NUM; i++)
|
for(i = 0; i < OETH_RXBD_NUM; i++)
|
{
|
{
|
bad=0;
|
bad=0;
|
| Line 728... |
Line 472... |
/* Process the incoming frame.
|
/* Process the incoming frame.
|
*/
|
*/
|
pkt_len = rx_bdp[i].len_status >> 16;
|
pkt_len = rx_bdp[i].len_status >> 16;
|
|
|
/* Do something here with the data - copy it into userspace, perhaps*/
|
/* Do something here with the data - copy it into userspace, perhaps*/
|
printk("\t end of packet\n\n");
|
|
|
|
|
|
/* finish up */
|
/* finish up */
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
|
rx_done++;
|
rx_done++;
|
| Line 764... |
Line 506... |
/* Probably good to check for TX errors here */
|
/* Probably good to check for TX errors here */
|
|
|
/* set our test variable */
|
/* set our test variable */
|
tx_done++;
|
tx_done++;
|
|
|
printk("T%d",i);
|
|
|
|
}
|
}
|
}
|
}
|
return;
|
return;
|
}
|
}
|
|
|
// A function and defines to fill and transmit a packet
|
// A function and defines to fill and transmit a packet
|
#define MAX_TX_BUFFER 1532
|
#define MAX_TX_BUFFER 1532
|
static char tx_buffer[MAX_TX_BUFFER];
|
static char tx_buffer[MAX_TX_BUFFER];
|
static unsigned long tx_data = 0x2ef2e242;
|
|
static inline char gen_next_tx_byte(void)
|
|
{
|
|
// Bit of LFSR action
|
|
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1));
|
|
//tx_data++;
|
|
return (char) tx_data & 0xff;
|
|
}
|
|
|
|
void
|
void
|
fill_and_tx_packet(int size)
|
fill_and_tx_packet(int size)
|
{
|
{
|
int i;
|
int i;
|
char tx_byte;
|
char tx_byte;
|
|
|
|
|
volatile oeth_regs *regs;
|
volatile oeth_regs *regs;
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
volatile oeth_bd *tx_bd;
|
volatile oeth_bd *tx_bd;
|
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
|
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
|
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
|
|
|
|
|
// If it's in use - wait
|
// If it's in use - wait
|
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
|
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
|
|
|
#ifndef _ETH_RXTX_DATA_H_
|
#ifndef _ETH_RXTX_DATA_H_
|
/* Copy the data into the transmit buffer, byte at a time */
|
|
|
// Use rand() function to generate data for transmission
|
|
// Assumption: ethernet buffer descriptors are 4byte aligned
|
char* data_b = (char*) tx_bd->addr;
|
char* data_b = (char*) tx_bd->addr;
|
for(i=0;i<size;i++)
|
// We will fill with words until there' less than a word to go
|
|
int words_to_fill = size/ sizeof(unsigned int);
|
|
unsigned int* data_w = (unsigned int*) data_b;
|
|
|
|
for(i=0;i<words_to_fill;i++)
|
|
data_w[i] = rand();
|
|
|
|
// Point data_b to offset wher word fills ended
|
|
data_b += (words_to_fill * sizeof(unsigned int));
|
|
|
|
int leftover_size = size - (words_to_fill * sizeof(unsigned int));
|
|
|
|
for(i=0;i<leftover_size;i++)
|
{
|
{
|
data_b[i] = gen_next_tx_byte();
|
data_b[i] = rand()&0xff;
|
}
|
}
|
#endif
|
#endif
|
|
|
tx_packet((void*)0, size);
|
tx_packet((void*)0, size);
|
}
|
}
|
|
|
//#define WAIT_PACKET_TX(x) while(tx_done<x)
|
int
|
#define WAIT_PACKET_TX(x)
|
main ()
|
|
|
int main ()
|
|
{
|
{
|
|
int i;
|
|
|
|
#ifdef _ETH_RXTX_DATA_H_
|
tx_data_pointer = 0;
|
tx_data_pointer = 0;
|
|
#endif
|
|
|
/* Initialise handler vector */
|
/* Initialise handler vector */
|
int_init();
|
int_init();
|
|
|
/* Install ethernet interrupt handler, it is enabled here too */
|
/* Install ethernet interrupt handler, it is enabled here too */
|
int_add(ETH0_IRQ, oeth_interrupt, 0);
|
int_add(ETH0_IRQ, oeth_interrupt, 0);
|
|
|
/* Enable interrupts in supervisor register */
|
/* Enable interrupts in supervisor register */
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
|
cpu_enable_user_interrupts();
|
|
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
|
|
|
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */
|
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */
|
tx_done = 0;
|
tx_done = 0;
|
rx_done = 0;
|
rx_done = 0;
|
|
|
int i;
|
|
ethphy_set_100mbit(0);
|
ethphy_set_100mbit(0);
|
|
|
#ifndef ETH_TX_TEST_LENGTH
|
#ifndef ETH_TX_TEST_LENGTH
|
# define ETH_TX_TEST_LENGTH 128
|
# define ETH_TX_START_LENGTH 40
|
|
# define ETH_TX_TEST_LENGTH 1024
|
|
# define ETH_TX_TEST_LENGTH_INCREMENT 21
|
//# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE
|
//# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE
|
#endif
|
#endif
|
|
|
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
|
for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
|
|
i+=ETH_TX_TEST_LENGTH_INCREMENT)
|
fill_and_tx_packet(i);
|
fill_and_tx_packet(i);
|
|
|
ethphy_set_10mbit(0);
|
ethphy_set_10mbit(0);
|
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
|
|
|
for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
|
|
i+=ETH_TX_TEST_LENGTH_INCREMENT)
|
fill_and_tx_packet(i);
|
fill_and_tx_packet(i);
|
|
|
exit(0x8000000d);
|
exit(0x8000000d);
|
|
|
|
|
