?rev1line? |
?rev2line? |
|
/*
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|
|
Tick timer interrupt test
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|
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We specify our own reset and initialisation routines as we don't link
|
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in the usual initialisation code.
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Based on original or1200 tick timer test
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|
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modified by
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|
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Julius Baxter, julius@opencores.org
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Tadej Markovic, tadej@opencores.org
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#define RAM_START RAM_BASE
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|
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/* Within the test we'll use following global variables:
|
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|
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r16 interrupt counter
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r17 current tick timer comparison counter
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r18 sanity counter
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r19 loop counter
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r20 temp value of SR reg
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r21 temp value of TTMR reg.
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r23 RAM_START
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r25-r31 used by int handler
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|
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The test do the following:
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We set up the tick timer to trigger once and then we trigger interrupts
|
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incrementally on every cycle in the specified test program; on
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interrupt handler we check if data computed so far exactly matches
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precalculated values. If interrupt has returned incorreclty, we can
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detect this using assertion routine at the end.
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*/
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Init the stack */
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.global _stack
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l.movhi r1, hi(_stack)
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l.ori r1, r1, lo(_stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* ================================================== [ tick interrupt ] === */
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.org 0x500
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.global _tick_handler
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_tick_handler:
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l.addi r31,r3,0
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# get interrupted program pc
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l.mfspr r25,r0,SPR_EPCR_BASE
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# calculate instruction address
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l.movhi r26,hi(_ie_start)
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l.ori r26,r26,lo(_ie_start)
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l.addi r3,r25,0 #print insn index
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l.nop 2
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l.sub r25,r25,r26
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l.addi r3,r25,0 #print insn index
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l.nop 2
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l.addi r3,r31,0 # restore r3
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l.sfeqi r25, 0x00
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l.bf _i00
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l.sfeqi r25, 0x04
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l.bf _i04
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l.sfeqi r25, 0x08
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l.bf _i08
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l.sfeqi r25, 0x0c
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l.bf _i0c
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l.sfeqi r25, 0x10
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l.bf _i10
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l.sfeqi r25, 0x14
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l.bf _i14
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l.sfeqi r25, 0x18
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l.bf _i18
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l.sfeqi r25, 0x1c
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l.bf _i1c
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l.sfeqi r25, 0x20
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l.bf _i20
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l.sfeqi r25, 0x24
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l.bf _i24
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l.sfeqi r25, 0x28
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l.bf _i28
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l.sfeqi r25, 0x2c
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l.bf _i2c
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l.sfeqi r25, 0x30
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l.bf _i30
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l.sfeqi r25, 0x34
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l.bf _i34
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l.sfeqi r25, 0x38
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l.bf _i38
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l.nop
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# value not defined
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_die:
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l.nop 2 #print r3
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l.addi r3,r0,0xeeee
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l.nop 2
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l.addi r3,r0,1
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l.jal exit
|
|
l.nop
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1:
|
|
l.j 1b
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|
l.nop
|
|
|
|
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/* =================================================== [ text section ] === */
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|
.section .text
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/* =================================================== [ start ] === */
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.global _start
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_start:
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.bf .L8
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l.nop
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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|
r14 contain block size
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate IC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.bf .L7
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l.add r6,r6,r14
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.nop
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|
l.nop
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|
l.nop
|
|
l.nop
|
|
l.nop
|
|
l.nop
|
|
l.nop
|
|
l.nop
|
|
|
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.L8:
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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|
l.bf .L10
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|
l.nop
|
|
/* Disable DC */
|
|
l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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|
/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate DC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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|
.L9:
|
|
l.mtspr r0,r6,SPR_DCBIR
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|
l.sfne r6,r5
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l.bf .L9
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|
l.add r6,r6,r14
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|
/* Enable DC */
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|
l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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.L10:
|
|
// Kick off test
|
|
l.jal _main
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|
l.nop
|
|
|
|
/* ========================================================= [ main ] === */
|
|
|
|
.global _main
|
|
_main:
|
|
#
|
|
# set tick counter to initial 3 cycles
|
|
#
|
|
l.addi r16,r0,0
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|
l.addi r17,r0,1
|
|
l.addi r18,r0,0
|
|
l.addi r19,r0,0
|
|
l.addi r22,r0,0
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|
|
|
l.movhi r23,hi(RAM_START)
|
|
l.ori r23,r23,lo(RAM_START)
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|
|
|
#
|
|
# unmask all ints
|
|
#
|
|
l.movhi r5,0xffff
|
|
l.ori r5,r5,0xffff
|
|
l.mtspr r0,r5,SPR_PICMR # set PICMR
|
|
|
|
# Set r20 to hold enable exceptions and interrupts
|
|
l.mfspr r20,r0,SPR_SR
|
|
l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
|
|
|
|
# Set r21 to hold value of TTMR
|
|
l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
|
|
l.add r21,r5,r17
|
|
|
|
#
|
|
# MAIN LOOP
|
|
#
|
|
_main_loop:
|
|
# reinitialize memory and registers
|
|
l.addi r3,r0,0xaaaa
|
|
l.addi r9,r0,0xbbbb
|
|
l.sw 0(r23),r3
|
|
l.sw 4(r23),r9
|
|
l.sw 8(r23),r3
|
|
|
|
# Reinitializes tick timer
|
|
l.addi r17,r17,1
|
|
l.mtspr r0,r0,SPR_TTCR # set TTCR
|
|
l.mtspr r0,r21,SPR_TTMR # set TTMR
|
|
l.mtspr r0,r0,SPR_TTCR # set TTCR
|
|
l.addi r21,r21,1
|
|
|
|
# Enable exceptions and interrupts
|
|
l.mtspr r0,r20,SPR_SR # set SR
|
|
|
|
##### TEST CODE #####
|
|
_ie_start:
|
|
l.movhi r3,0x1234 #00
|
|
l.sw 0(r23),r3 #04
|
|
l.movhi r3,hi(RAM_START) #08
|
|
l.lwz r3,0(r3) #0c
|
|
l.movhi r3,hi(RAM_START) #10
|
|
l.addi r3,r3,4 #14
|
|
l.j 1f #18
|
|
l.lwz r3,0(r3) #1c
|
|
l.addi r3,r3,1 #20
|
|
1:
|
|
l.sfeqi r3,0xdead #24
|
|
l.jal 2f #28
|
|
l.addi r3,r0,0x5678 #2c
|
|
|
|
_return_addr:
|
|
2:
|
|
l.bf _die #30
|
|
l.sw 8(r23),r3 #34
|
|
_ie_end:
|
|
l.nop #38
|
|
##### END OF TEST CODE #####
|
|
|
|
# do some testing
|
|
|
|
l.j _main_loop
|
|
l.nop
|
|
|
|
_i00:
|
|
l.sfeqi r3,0xaaaa
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i04:
|
|
l.movhi r26,0x1234
|
|
l.sfeq r3,r26
|
|
l.bnf _die
|
|
l.nop
|
|
l.lwz r26,0(r23)
|
|
l.sfeqi r26,0xaaaa
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i08:
|
|
l.movhi r26,0x1234
|
|
l.sfeq r3,r26
|
|
l.bnf _die
|
|
l.nop
|
|
l.lwz r27,0(r23)
|
|
l.sfeq r27,r26
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i0c:
|
|
l.sfeq r3,r23
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i10:
|
|
l.movhi r26,0x1234
|
|
l.sfeq r26,r3
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i14:
|
|
l.sfeq r3,r23
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i18:
|
|
l.addi r26,r23,4
|
|
l.sfeq r3,r26
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i1c:
|
|
l.j _die
|
|
l.nop
|
|
_i20:
|
|
l.j _die
|
|
l.nop
|
|
_i24:
|
|
l.mfspr r26,r0,SPR_ESR_BASE
|
|
l.addi r30,r3,0
|
|
l.addi r3,r26,0
|
|
l.nop 2
|
|
l.addi r3,r30,0
|
|
l.andi r26,r26,SPR_SR_F
|
|
l.sfeq r26,r0
|
|
l.bf _die
|
|
l.nop
|
|
l.sfeqi r3,0xbbbb
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i28:
|
|
l.mfspr r26,r0,SPR_ESR_BASE
|
|
l.addi r30,r3,0
|
|
l.addi r3,r26,0
|
|
l.nop 2
|
|
l.addi r3,r30,0
|
|
l.andi r26,r26,SPR_SR_F
|
|
l.sfeq r26,r0
|
|
l.bnf _die
|
|
l.nop
|
|
l.sfeqi r22,1
|
|
l.bf _resume
|
|
l.addi r22,r0,1
|
|
l.sfeqi r9,0xbbbb
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i2c:
|
|
l.movhi r26,hi(_return_addr)
|
|
l.ori r26,r26,lo(_return_addr)
|
|
l.sfeq r9,r26
|
|
l.bnf _die
|
|
l.nop
|
|
l.sfeqi r3,0xbbbb
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i30:
|
|
l.sfeqi r3,0x5678
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i34:
|
|
l.sfeqi r3,0x5678
|
|
l.bnf _die
|
|
l.nop
|
|
l.lwz r26,8(r23)
|
|
l.sfeqi r26,0xaaaa
|
|
l.bnf _die
|
|
l.nop
|
|
l.j _resume
|
|
l.nop
|
|
_i38:
|
|
l.lwz r26,8(r23)
|
|
l.sfeqi r26,0x5678
|
|
l.bnf _die
|
|
l.nop
|
|
#
|
|
# mark finished ok
|
|
#
|
|
l.movhi r3,hi(0xdeaddead)
|
|
l.ori r3,r3,lo(0xdeaddead)
|
|
l.nop 2
|
|
l.movhi r3,hi(0x8000000d)
|
|
l.ori r3,r3,lo(0x8000000d)
|
|
l.nop 2
|
|
l.addi r3,r0,0
|
|
|
|
l.jal exit
|
|
l.nop
|
|
_ok:
|
|
l.j _ok
|
|
l.nop
|
|
|
|
_resume:
|
|
l.mfspr r27,r0,SPR_ESR_BASE
|
|
l.addi r26,r0,SPR_SR_TEE
|
|
l.addi r28,r0,-1
|
|
l.xor r26,r26,r28
|
|
l.and r26,r26,r27
|
|
l.mtspr r0,r26,SPR_ESR_BASE
|
|
|
|
l.rfe
|
|
l.addi r3,r3,5 # should not be executed
|
