OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Diff between revs 472 and 486

Show entire file | Details | Blame | View Log

Rev 472 Rev 486
Line 1... Line 1...
 
2011-01-27  Jeremy Bennett  
 
 
 
        * configure: Regenerated.
 
        * configure.ac: Updated version.
 
        * cpu/or32/insnset.c : Added behavior for NOP_RANDOM and
 
        NOP_OR1KSIM. Removed default behavior.
 
        * cpu/or1k/spr-defs.h: Added definition of NOP_RANDOM and
 
        NOP_OR1KSIM. Removed definitions of NOP_REPORT_FIRST and
 
        NOP_REPORT_LAST.
 
        * doc/or1ksim.texi : Document l.nop 10 and
 
        l.nop 11.
 
        * libtoplevel.c (or1ksim_init): Replaced srand () by
 
        init_randomness ().
 
        * peripheral/memory.c (mem_reset): Do not allow general reset of
 
        random number generator.
 
        * sim_config.c (parse_args): Change use of rand () to random ().
 
        * toplevel.c (main): Replaced srand () by init_randomness ().
 
        * toplevel-profile.c (main): Replaced srand () by init_randomness ().
 
        * toplevel-support.c (init_randomness): Created.
 
        * toplevel-support.h : Added.
 
 
2011-01-05  Jeremy Bennett 
2011-01-05  Jeremy Bennett 
 
 
        * cpu/common/abstract.c (diassemble_instr): Added instruction
        * cpu/common/abstract.c (diassemble_instr): Added instruction
        as third parameter. No longer look up in memory.
        as third parameter. No longer look up in memory.
        * cpu/common/abstract.h : Updated prototype.
        * cpu/common/abstract.h : Updated prototype.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.